Patents by Inventor Ting Chen

Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978781
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Anhao Cheng, Fang-Ting Kuo, Yen-Yu Chen
  • Patent number: 11977221
    Abstract: An optical device for aberration correction (e.g., chromatic aberration correction) is disclosed. The optical device includes an optical component (e.g., a spherical lens) and a metasurface optically coupled to the optical component. The metasurface includes a plurality of nanostructures that define a phase profile. The phase profile corrects an aberration (e.g., chromatic aberration) caused by the optical component. The resulting optical device becomes diffraction-limited (e.g., for the visible spectrum) with the metasurface.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 7, 2024
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Wei-Ting Chen, Alexander Yutong Zhu, Jared F. G. Sisler, Federico Capasso
  • Patent number: 11976776
    Abstract: A stand adjustment device has a tripod-connecting member, a connecting seat, a proximal clamping plate, a boom-connecting tube, a locking shaft, and a manual operating member. The connecting seat is rotatably located around the tripod-connecting member. The proximal clamping plate is detachably attached to a side of the connecting seat. One end of the locking shaft is movably disposed in the boom-connecting tube. The boom is slidably mounted through the boom-connecting tube and the locking shaft. The locking shaft is slidably mounted through the boom-connecting tube, the proximal clamping plate, and the connecting seat such that the boom-connecting tube is rotatable relative to the connecting seat. The manual operating member and the locking shaft are configured to clamp the boom-connecting tube, the proximal clamping plate, and the connecting seat therebetween into a locked condition.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: May 7, 2024
    Assignee: RELIANCE INTERNATIONAL CORP.
    Inventors: Pei-Chi Chu, Cheng-Lin Ho, Chi-Chia Huang, Wei-Ting Chen
  • Patent number: 11980041
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20240145412
    Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.
    Type: Application
    Filed: November 27, 2022
    Publication date: May 2, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Che Huang, Chao-Ting Chen, Jui-Fa Lu, Chi-Heng Lin
  • Publication number: 20240145867
    Abstract: A separator for a lithium battery and a method for manufacturing the same are provided. The separator includes a substrate layer and a coating layer. The substrate layer is a polyolefin porous film and has a substrate thickness ranging from 10 to 30 micrometers. The coating layer is coated on the substrate layer, and has a coating layer thickness ranging from 1 to 5 micrometers. The coating layer includes a heat-resistant resin material and a plurality of inorganic ceramic particles glued in the heat-resistant resin material. The heat-resistant resin material has a melting point (Tm) or a glass transition temperature (Tg) of not less than 150° C. An average particle size of the inorganic ceramic particles is 10% to 40% of the coating layer thickness of the coating layer. The inorganic ceramic particles are stacked in the coating layer with a height of at least three layers.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 2, 2024
    Inventors: TE-CHAO LIAO, CHUN-CHE TSAO, CHENG-HUNG CHEN, LI-TING WANG
  • Publication number: 20240147646
    Abstract: A portable data accessing device and more particularly the use of multi-port interfaces on a data accessing device disclosed. The multi-port data accessing device includes an inner body, one or a plurality of moving-caps, one or a plurality of grips, a pump-action and one or a plurality of locking/releasing mechanisms.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Yi-Ting Lin, Hsien-Chih Chang, Chang-Hsing Lin, Hao-Yin Lo, Ben Wei Chen
  • Publication number: 20240141070
    Abstract: Provided is an isolated antigen-binding protein, wherein the drug is used for the treatment of tumor, and the isolated antigen-binding protein comprises a PD-L1 binding moiety and an OX40 binding moiety, wherein: the OX40 binding moiety is capable of recognizing and/or binding amino acid residues G70 and/or F71 in a human OX40 extracellular domain; and the PD-L1 binding moiety is capable of recognizing and/or binding amino acid residues I54, Y56, E58, Q66 and/or R113 in an N-terminal IgV domain of human PD-L1. Further provided is a use of the isolated antigen-binding protein in preparing a drug, wherein the drug is used for the treatment of tumors.
    Type: Application
    Filed: October 16, 2020
    Publication date: May 2, 2024
    Inventors: Ting XU, Pilin WANG, Kangping GUO, Yuhao JIN, Ting CHEN, Li GAO, Qingqing ZHANG
  • Publication number: 20240143538
    Abstract: The invention provides an interface conversion device including a USB connector, a DP connector, a first physical layer (PHY) circuit, a second PHY circuit, a digital buffer, a USB controller, and a path switching circuit. A first terminal of the first PHY circuit is coupled to the USB connector. The digital buffer and the USB controller are coupled to a second terminal of the first PHY circuit. A first terminal of the second PHY circuit is coupled to the DP connector. The path switching circuit selectively electrically connects a second terminal of the second PHY circuit to an output terminal of the digital buffer when the interface conversion device is operated in DP ALT mode. The path switching circuit selectively electrically connects the second terminal of the second PHY circuit to a DP output terminal of the USB controller when the interface conversion device is operated in tunneling mode.
    Type: Application
    Filed: December 20, 2022
    Publication date: May 2, 2024
    Applicant: GENESYS LOGIC, INC.
    Inventor: Wai-Ting Chen
  • Publication number: 20240141922
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240144868
    Abstract: The present disclosure provides a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
  • Publication number: 20240147405
    Abstract: A controlling method for a wireless communication device is provided. The controlling method for the wireless communication device includes: attaching a first Universal Subscriber Identity Module (USIM) to a Long-Term Evolution (LTE) network; determining whether a second USIM is camped on the LTE network; detecting whether a paging collision is happened, if the second USIM is camped on the LTE network; generating a requested International Mobile Subscriber Identity (IMSI) offset for the second USIM, if the paging collision is happened, wherein the requested IMSI offset is 1 or min(T, nB)?1, T is a default paging period and nB is a number of paging occurrences within the default paging period; transmitting an attach request with the requested IMSI offset to the LTE network for the second USIM; receiving a negotiated IMSI offset from the LTE network; and attaching the second USIM to the LTE network with the negotiated IMSI offset.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Yu LIN, Ya-ling Hsu, Wan-Ting Huang, Yi-Han CHUNG, Yi-Cheng CHEN
  • Patent number: 11972956
    Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
  • Patent number: 11971609
    Abstract: A photographing optical system includes eight lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The eight lens elements each have an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has positive refractive power. The fifth lens element has positive refractive power. The object-side surface of the seventh lens element is convex in a paraxial region thereof. The image-side surface of the eighth lens element is concave in a paraxial region thereof. At least one lens surface of at least one lens element of the photographing optical system has at least one critical point in an off-axis region thereof.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: April 30, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chun-Yen Chen, Kuan-Ting Yeh, Tzu-Chieh Kuo
  • Publication number: 20240138098
    Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Yu-Ming Lin
  • Publication number: 20240136117
    Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.
    Type: Application
    Filed: October 1, 2023
    Publication date: April 25, 2024
    Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HANG-CHUN LU, YA-WEN YANG, YU-TING HSU, WEI-ZHI HUANG
  • Publication number: 20240135990
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Publication number: 20240135897
    Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.
    Type: Application
    Filed: December 11, 2022
    Publication date: April 25, 2024
    Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
  • Publication number: 20240130614
    Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 25, 2024
    Inventors: Shao Hung HUANG, Chao-Ting CHEN, Fong Hao KUO, Yu-Chung TUNG, Chu-Ming CHENG, Chi-Yuan KANG