Abstract: Provided are a channel configuration method and terminal, a storage medium and an electronic device. The method includes: determining that multiple physical channels overlap in a time domain; and selecting a designated channel to carry information or data in the multiple physical channels.

Abstract: A method for optimizing a blind detection capability is performed by a terminal, and includes: determining blind detection capability information, wherein the blind detection capability information includes a maximum number of physical downlink control channel (PDCCH) candidates monitored in n time slots under a first subcarrier spacing, and a maximum number of non-overlapped control channel elements (CCEs) in the n time slots under the first subcarrier spacing, where n is an integer greater than 1.

Abstract: A method for sending uplink transmission includes: sending, in response to detecting presence of a time interval within a channel occupancy time (COT) of an unlicensed spectrum, a predetermined uplink transmission within the time interval.

Abstract: The present disclosure discloses a method for lane alignment detection based on millimeter wave radar data. An embodiment of the method comprises: acquiring the vehicle trajectory data and radar reflection data detected by the millimeter wave radar which are installed on the road to sense the moving vehicles; setting up two datasets in the database, including vehicle track dataset and waypoint dataset obtained after rasterizing the road; filtering vehicle track data and vehicle radar reflection data detected by millimeter-wave radar and eliminate erroneous data; performing radial clustering and horizontal initial stable point clustering on the filtered data; extracting and outputting the lane alignment. Compared with the prior art, the invention possesses the advantages of obtaining more accurate lane alignments, low cost and good adaptability, etc.

Abstract: A method for determining a resource location includes: determining a first resource location of a paging occasion; and determining, according to the first resource location, a second resource location of a reference signal for an idle terminal.

Abstract: A method for determining HARQ feedback delay is performed by a base station, and includes: determining a target set of HARQ feedback delays among more than one set of HARQ feedback delays, which are predefined in a protocol and correspond to downlink control information (DCI) of a preset format; wherein the more than one set of HARQ feedback delays correspond to different subcarrier bandwidths; and sending the DCI of the preset format configured to indicate a target delay value, to a terminal, wherein the target delay value is one of more than one delay value included in the target set of HARQ feedback delays.

Abstract: A communication method, includes: receiving first configuration information, wherein the first configuration information includes a set of feedback delay indication values for a hybrid automatic repeat request acknowledgment, the set of feedback delay indication values is a subset of a set of candidate feedback delay indication values for the hybrid automatic repeat request acknowledgment, and the set of candidate feedback delay indication values includes an integer greater than 15.

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.

Abstract: The present application relates to the field of communication technology. Disclosed by the embodiments of the present application are a method and device for determining and receiving resources, an electronic device, and a storage medium. The method for determining resources includes: multiplexing a plurality of Hybrid Automatic Repeat reQuest Acknowledgement (HARQ-ACK) codebooks in a designated Physical Uplink Control Channel (PUCCH) resource. The designated PUCCH resource at least includes one of: a PUCCH resource determined according to a PUCCH resource indicator (PRI) in last Downlink Control Information (DCI) of DCI corresponding to a Downlink Physical Shared Channel (PDSCH) corresponding to a HARQ-ACK codebook having a higher priority in the plurality of HARQ-ACK codebooks, and a PUCCH resource corresponding to the HARQ-ACK codebook having the higher priority in the plurality of HARQ-ACK codebooks.

Abstract: A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.

Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: Provided are a method and apparatus for transmission processing and a computer-readable storage medium. The method includes determining for at least two transmissions that the starting position of a first transmission is earlier than a point G; and transmitting the first transmission from the starting position of the first transmission to the point G, or transmitting the first transmission from the starting position of the first transmission to the ending position of the first transmission. The point G is a time point of first preset time before the starting position of a second transmission.