Abstract: A chip package with electromagnetic interference (EMI) shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), an insulating layer, and an electromagnetic interference (EMI) shielding layer. A peripheral wall is formed around at least one first opening of the insulating layer for enclosing the first opening and a flat portion is disposed around the peripheral wall while a level of the flat portion is lower than a level of the peripheral wall. The flat portion of the insulating layer is covered with the EMI shielding layer which is isolated and electrically insulated from a pad in the first opening by the peripheral wall of the insulating layer. Thereby problems of the chip including fast increase in temperature and electromagnetic interference can be solved effectively.

Abstract: A chip package which includes a glass fiber substrate made of FR-4 fiberglass is provided. The chip package further includes a substrate pad which is a stacked metal structure with a certain thickness and composed of a nickel layer, a palladium layer, and a gold layer, or a nickel layer and a gold layer stacked over at least one first circuit layer in turn. A total thickness of the substrate pad is 3.15-5.4 ?m. The glass fiber substrate and the substrate pad can bear positive pressure generated during wire bonding. Thereby at least one solder joint is formed on the substrate pad precisely and integrally. This helps reduction in material cost for manufacturers.

Abstract: A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.

Abstract: A chip package with at least one electromagnetic interference (EMI) shielding layer and at least one ground wire and a method of manufacturing the same are provided. The chip package includes a chip package unit, at least one EMI shielding layer, and at least one ground wire. The ground wire which consists of a first end and a second end opposite to the first end is inserted through the EMI shielding layer and a first insulating layer of the chip package unit. The first end is electrically connected with the EMI shielding layer while the second end of the ground wire is electrically connected with at least one grounding end of at least one first circuit layer of the chip package unit for protection against static electricity. Thereby malfunction of an electronic system with semiconductor chips due to static electricity can be avoided.

Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.

Abstract: A chip package having four sides provided with electromagnetic interference (EMI) shielding layers correspondingly and a method of manufacturing the same are provided. The four EMI shielding layers are made of metals, located on four lateral sides of the chip package, and completely covering four lateral sides of a substrate and four lateral sides of an insulating layer to prevent at least one first circuit layer, at least one second circuit layer, and at least one chip from electromagnetic interference. Moreover, the EMI shielding layers help to improve heat dissipation efficiency of the first circuit layer, the second circuit layer, and the chip.

Abstract: A chip package with an electromagnetic interference shielding layer and a method of manufacturing the same are provided. The chip package includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one chip, a first insulating layer, and at least one electromagnetic interference shielding layer. The electromagnetic interference shielding layer is made of metals and covering a first surface of the first insulating layer completely for preventing the respective first circuit layers, the respective second circuit layers, and the respective chips from external electromagnetic interference (EMI).

Abstract: A chip package unit, a method of manufacturing the same, and package structure formed by stacking the same are provided. At least one first connecting pad, at least one second connecting pad, and at least one third connecting pad of a flexible printed circuit (FPC) board in the chip package unit are electrically connected with one another by circuit of the FPC board. At least one die pad disposed on a front surface of a chip is electrically connected with the first connecting pad first and then electrically connected with the outside by the second connecting pad or the third connecting pad. Thereby the chip of the chip package unit can be electrically connected with the outside by the front surface or a back surface thereof. Therefore, not only production is reduced due to simplified production process and energy saved, volume of the package structure is also reduced.

Abstract: A chip package unit, a method of manufacturing the same, and a package structure formed by stacking the same are provided. The chip package unit is formed by cutting of a wafer separately. The chip package unit includes a chip, a first redistribution layer (RDL), a second RDL, and at least one first circuit layer. The first circuit layer is electrically connected with and disposed between a first conductive circuit and a second conductive circuit. The first circuit layer is located at least one first lateral side of the chip, at least one second lateral side of the first RDL, and at least one third lateral side of the second RDL. The chip can be electrically connected with the outside by the first conductive circuit or the second conductive circuit. Thereby manufacturing process is simplified and manufacturing cost is further reduced.

Abstract: The present application discloses a thinning system in package featuring an encapsulation structure in which no printed circuit board exists and comprising: a plurality of dies mounted on a top face of a copper holder and electrically connected to the plurality of data pins on the copper holder; a passive element mounted on the top face and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder and both the dies and the passive element are fixed on the top face of the copper holder through a layer of insulation adhesives; a molding compound encasing the dies and the passive element on the top face of the copper holder.

Abstract: A multi-layer stacked chip package is provided. A first substrate, a first circuit layer, a first chip, and a first insulation layer form a lower layer chip package while a second substrate, a second circuit layer, a second chip, and a second insulation layer form an upper layer chip package. The upper layer chip package is stacked over the lower layer chip package so that the multi-layer stacked chip package is formed by such stacking mode. One of the at least two chips is used to operate the rest chips or computing functions of the respective chips are combined to increase overall computing performance.

Abstract: A chip package which includes a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive circuit, and at least one third dielectric layer is provide. The conductive circuit is formed by highly concentrated silver paste or copper paste filled in at least one first groove of the first dielectric layer and at least one second groove of the second dielectric layer while at least one die pad of the chip is electrically connected with the conductive circuit for improving electrical conduction efficiency of the conductive circuit. Moreover, at least one die-pad bump is formed in the first groove, arranged at and electrically connected with a surface of the die pad for protecting of the die pad.

Abstract: A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 ?m to 20 ?m. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.

Abstract: A bump of a chip package with higher bearing capacity in wire bonding is provided. The at least one bump of the chip package is a metal stacked member with a certain thickness. An overall thickness of the bump is 4.5-20 ?m. Thereby a structural strength of the bump is improved and thus able to bear positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under at least one die pad or arrange under the die pad of the chip. Thereby increased cost problem caused by internal circuit redesign of the chip can be solved and this helps to reduce cost at manufacturing end.

Abstract: A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.

Abstract: The present application discloses an integration package with insulating boards, which features an insulating board structure replacing a plurality of printed circuit boards and packaging materials in a conventional POP structure and comprises a base substrate, a basic circuit and at least an electronic component: the basic circuit is exposed on an upper surface of the base substrate; the electronic component and the basic circuit are electrically connected with each other; both the base substrate and the electronic component are thermally compressed and covered by a first insulating board.

Abstract: Provided are a digital battery separator and a preparation method therefor. The digital battery separator comprises a base membrane (1) and a polymer coating (2) coating at least one surface of the base membrane (1), wherein the thickness of the separator is 3-10 ?m, and the ionic conductivity of the separator is 0.704-4.70 mS·cm?1. A thinner and safer battery separator with a smaller resistance, better porosity and air permeability, and better heat resistance is obtained, The problems such as being unsafe, having a large resistance, having low porosity, poor air permeability and poor heat resistance that are present in an existing ultrathin separator are solved.

Abstract: The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.

Abstract: Disclosed herein are a catalyst composition, catalyst devices, and methods for removing formaldehyde, volatile organic compounds, and other pollutants from an air flow stream. The catalyst composition including manganese oxide, optionally one or more of alkali metals, alkaline earth metals, zinc, iron, binder, an inorganic oxide, or carbon.

Abstract: The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.