Patents by Inventor Ting Ku

Ting Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240036854
    Abstract: A method and an electronic device of updating and testing multiple embedded controllers (ECs) are provided. First, in the electronic device, a basic input output system (BIOS) executes an updating software to read an embedded-controller read-only file (ECROF) in an external read-only memory (ROM). A first embedded controller (first EC) writes the ECROF from the external ROM into the first EC. The first EC uses the ECROF to update a first firmware of the first EC. Then, the first EC updates a second firmware of a second embedded controller (second EC) with the ECROF. Next, the first EC or another hardware device compares the first summary information stored in the first EC and the second summary information of the updated second EC. When the first summary information and the second summary information are different, the first EC or the hardware device generates a warning message.
    Type: Application
    Filed: October 21, 2022
    Publication date: February 1, 2024
    Inventors: MING-LUN YANG, TING-KU TUNG, YUNG-HSIEN HO
  • Patent number: 11804708
    Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 31, 2023
    Assignee: NVIDIA CORP.
    Inventors: Jauwen Chen, Sunitha Venkataraman, Ting Ku
  • Patent number: 11777483
    Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: October 3, 2023
    Assignee: NVIDIA Corporation
    Inventors: Nishit Harshad Shah, Ting Ku, Krishnamraju Kurra, Gunaseelan Ponnuvel, Tezaswi Raja, Suhas Satheesh
  • Publication number: 20230299760
    Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventors: Nishit Harshad SHAH, Ting KU, Krishnamraju KURRA, Gunaseelan PONNUVEL, Tezaswi RAJA, Suhas SATHEESH
  • Publication number: 20230237313
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: NVIDIA Corp.
    Inventors: Haoxing Ren, George Ferenc Kokai, Ting Ku, Walker Joseph Turner
  • Patent number: 11651194
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 16, 2023
    Assignee: NVIDIA Corp.
    Inventors: Haoxing Ren, George Kokai, Ting Ku, Walker Joseph Turner
  • Patent number: 11619661
    Abstract: In various embodiments, a current measurement circuit measures an input current within an integrated circuit. The current measurement circuit includes an integration capacitor, an operational amplifier, a comparison capacitor, an inverter, and multiple switches. The current measurement circuit is coupled to a clocking circuit that, during operation, generates a two-phase clock having a frequency that is proportional to the input current. At least a portion of the switches are turned on during a first phase of the two-phase clock and are turned off during a second phase of the two-phase clock.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 4, 2023
    Assignee: NVIDIA Corporation
    Inventors: Nishit Harshad Shah, Ting Ku, Krishnamraju Kurra, Gunaseelan Ponnuvel, Tezaswi Raja, Suhas Satheesh
  • Patent number: 11395400
    Abstract: A display device includes a driving substrate, a front panel laminate, a circuit board, a front protective layer, and a glue. The front panel laminate is disposed on the driving substrate and includes a display medium layer. The circuit board is disposed on an end of the driving substrate. The front protective layer is disposed on the front panel laminate. The front protective layer has a notch. An end of the circuit board is in the notch. The end of the circuit board and the front protective layer have a first gap therebetween. The glue is filled in the first gap. A normal projection of the glue on the driving substrate overlaps a normal projection of the circuit board on the driving substrate and overlaps a normal projection of the front protective layer on the driving substrate.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 19, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Yu-Ting Ku, Tzu-Yu Cheng
  • Publication number: 20210281067
    Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Applicant: NVIDIA Corp.
    Inventors: Jauwen Chen, Sunitha Venkataraman, Ting Ku
  • Publication number: 20210158127
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Application
    Filed: April 27, 2020
    Publication date: May 27, 2021
    Applicant: NVIDIA Corp.
    Inventors: Haoxing Ren, George Kokai, Ting Ku, Walker Joseph Turner
  • Publication number: 20210029820
    Abstract: A display device includes a driving substrate, a front panel laminate, a circuit board, a front protective layer, and a glue. The front panel laminate is disposed on the driving substrate and includes a display medium layer. The circuit board is disposed on an end of the driving substrate. The front protective layer is disposed on the front panel laminate. The front protective layer has a notch. An end of the circuit board is in the notch. The end of the circuit board and the front protective layer have a first gap therebetween. The glue is filled in the first gap. A normal projection of the glue on the driving substrate overlaps a normal projection of the circuit board on the driving substrate and overlaps a normal projection of the front protective layer on the driving substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: January 28, 2021
    Inventors: Yu-Ting KU, Tzu-Yu CHENG
  • Patent number: 8793091
    Abstract: A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: July 29, 2014
    Assignee: Nvidia Corporation
    Inventors: Ting Ku, Shifeng Yu, Brian Smith
  • Patent number: 8523742
    Abstract: A baby walker is introduced herein. The baby walker includes a base and a pair of shoulder straps. The base is made by flexible materials such as plastics, or the similar materials. In one exemplary embodiment, the base of the baby walker may be packaged in a deflated form, and may be filled with air to form a shape as desired for an operation mode. The baby walker further includes a pair of shoulder straps which are firmly and fixedly attached in a peripheral upper side of the base. When the baby is placed in a central cavity of the base, the pair of the shoulder straps can be placed alongside the two shoulders of the baby. When the baby wears the baby walker and stands up, the whole baby walker is lifted up for a height above the ground level.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: September 3, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Peter Ar-Fu Lam, Chun-Ting Lee, Ting-Ku Tao
  • Publication number: 20120053022
    Abstract: A baby walker is introduced herein. The baby walker includes a base and a pair of shoulder straps. The base is made by flexible materials such as plastics, or the similar materials. In one exemplary embodiment, the base of the baby walker may be packaged in a deflated form, and may be filled with air to form a shape as desired for an operation mode. The baby walker further includes a pair of shoulder straps which are firmly and fixedly attached in a peripheral upper side of the base. When the baby is placed in a central cavity of the base, the pair of the shoulder straps can be placed alongside the two shoulders of the baby. When the baby wears the baby walker and stands up, the whole baby walker is lifted up for a height above the ground level.
    Type: Application
    Filed: September 1, 2010
    Publication date: March 1, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Peter Ar-Fu Lam, Chun-Ting Lee, Ting-Ku Tao
  • Patent number: 7976185
    Abstract: A light emitting diode (LED) lamp tube includes a lamp device including a circuit board, and a plurality of LEDs mounted on the circuit board. The circuit board is disposed in a tubular enclosure such that an inner peripheral surface of the enclosure is divided into a non-illuminated portion and a light-receiving portion. The tubular enclosure has a plurality of tapered protrusions extending from the light-receiving portion toward the LEDs. Each of the tapered protrusions converges from the light-receiving portion toward the LEDs. Each of the tapered protrusions further has a maximum width at an outer end thereof, which increases gradually from a middle portion of the light-receiving portion toward junctions of the light-receiving portion and the non-illuminated portion.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 12, 2011
    Assignee: I Shou University
    Inventors: Chii-Maw Uang, Huei-Ting Ku
  • Patent number: 7936126
    Abstract: A light emitting diode (LED) lamp tube includes a circuit board and a tubular enclosure. The circuit board is disposed in the enclosure such that the enclosure is divided into a non-illuminated portion and a light-receiving portion. The light-receiving portion has two light-condensing side sections corresponding respectively to two sides of the circuit board, and a light-diffusing middle section connected between the light-condensing side sections. An outer surface of the light-receiving portion has a smoothly varying curvature. The light-condensing side sections cooperate with the light-diffusing middle section to diffuse uniformly LED light transmitted from an outer surface of the enclosure.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: May 3, 2011
    Assignee: I Shou University
    Inventors: Chii-Maw Uang, Huei-Ting Ku
  • Publication number: 20100072877
    Abstract: A light emitting diode (LED) lamp tube includes a circuit board and a tubular enclosure. The circuit board is disposed in the enclosure such that the enclosure is divided into a non-illuminated portion and a light-receiving portion. The light-receiving portion has two light-condensing side sections corresponding respectively to two sides of the circuit board, and a light-diffusing middle section connected between the light-condensing side sections. An outer surface of the light-receiving portion has a smoothly varying curvature. The light-condensing side sections cooperate with the light-diffusing middle section to diffuse uniformly LED light transmitted from an outer surface of the enclosure.
    Type: Application
    Filed: July 10, 2009
    Publication date: March 25, 2010
    Applicant: I Shou University
    Inventors: Chii-Maw Uang, Huei-Ting Ku
  • Publication number: 20100067230
    Abstract: A light emitting diode (LED) lamp tube includes a lamp device including a circuit board, and a plurality of LEDs mounted on the circuit board. The circuit board is disposed in a tubular enclosure such that an inner peripheral surface of the enclosure is divided into a non-illuminated portion and a light-receiving portion. The tubular enclosure has a plurality of tapered protrusions extending from the light-receiving portion toward the LEDs. Each of the tapered protrusions converges from the light-receiving portion toward the LEDs. Each of the tapered protrusions further has a maximum width at an outer end thereof, which increases gradually from a middle portion of the light-receiving portion toward junctions of the light-receiving portion and the non-illuminated portion.
    Type: Application
    Filed: July 10, 2009
    Publication date: March 18, 2010
    Applicant: I Shou University
    Inventors: Chii-Maw Uang, Huei-Ting Ku
  • Publication number: 20100067225
    Abstract: A light emitting diode (LED) lamp tube includes a tubular enclosure extending along an axial direction and having an inner peripheral surface. A lamp device is disposed in the enclosure, and includes a circuit board, and a plurality of LEDs electrically connected to the circuit board. Two connectors are disposed respectively at two ends of the enclosure and are electrically connected to the circuit board. The connectors are adapted to be electrically connected to a power source. An optical film unit is disposed on the inner peripheral surface of the enclosure. The optical film unit has a film body and a plurality of protrusions arranged along the axial direction and protruding from the film body toward the inner peripheral surface of the enclosure.
    Type: Application
    Filed: July 10, 2009
    Publication date: March 18, 2010
    Applicant: I Shou University
    Inventors: Chii-Maw Uang, Huei-Ting Ku
  • Publication number: 20090259425
    Abstract: A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Applicant: NVIDIA CORPORATION
    Inventors: Ting Ku, Shifeng Yu, Brian Smith