Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: An expander coupled between at least a first and second SCSI device for transmitting data and training patterns is provided. The expander includes, a first detection module for detecting a training pattern received from the first device; a second detection module that detects when a first section of the training pattern has been transmitted to the second device; and means for changing the expander's mode from a training mode to a repeat mode after the first section.

Abstract: A transceiver circuit for transmitting a data signal over a communications bus at a predefined bit rate includes a transmitter. The data signal is a digital signal having first and second logic levels. The transmitter receives and modifies the data signal and feeds the modified data signal to the communications bus. The transmitter includes a drive circuit and an output circuit. The drive circuit receives the data signal and a clock signal and generates control signals which depend on the logic level of the data signal. The control signals are sequentially generated when the data signal has consecutive bits of the same logic level. The output circuit receives the control signals and the data signal and generates an output signal which corresponds to the data signal, but which has a varying drive strength determined by the control signals.

Abstract: An interface module for a communications system includes a processing device and a peripheral device which are interconnected through a communications bus. The interface module includes a transceiver interface and a protection circuit. The protection circuit is positioned between the transceiver interface and a port configured to receive a signal from a terminal of the communications bus. The protection circuit is further configured to automatically provide a protection voltage to the transceiver interface if a power supply for the transceiver interface is inactive. The protection voltage is derived from the signal received at the terminal.

Abstract: A state dependent synchronization circuit synchronizes an asynchronous input signal to a clock signal to generate a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also maintains the state of the output signal at a level corresponding to the input signal when the input signal does not change. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not charge state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal.