Abstract: An electric signal reconstruction system includes a signal generator and a computing element. The signal generator has a time constant and is configured to generate a plurality of signal value corresponding to a plurality of time points within a time period, wherein the signal values include a designated value, the time points include a designated time point, and the designated value corresponds to the designated time point. The computing element is electrically connected to the signal generator and is configured to perform operations including: performing a differential calculation or an integral calculation according to the time points and the signal values to generate a fundamental value; calculating a correction constant associated with the time constant; calculating a product of the correction constant and the fundamental value as a correction value; calculating a sum of the correction value and the designated value as a reconstruction value; and outputting the reconstruction value.

Abstract: A sample message processing method and apparatus. The method includes: acquiring interface data generated during a process of performing data interaction by means of an interface; determining additional data corresponding to the interface data; on the basis of the additional data, generating identification data corresponding to the interface data; if the identification data matches historical identification data, determining a request message and a response message, which correspond to message version data, as a historical sample message pair; and if the identification data does not match the historical identification data, determining the request message and the response message, which correspond to the message version data, as a new sample message pair, such that a sample message pair can be formed on the basis of the interface data.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Abstract: A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.

Abstract: A semiconductor device can be applied to a memory device. The semiconductor device of the disclosure includes a voltage sensor, a convertor and a command/address on-die-termination (CA_ODT) circuit. The voltage sensor receives a voltage setting command, and sense a voltage level of the voltage setting command to generate a sensing signal. The convertor generates a setting signal in response to the sensing signal. The CA_ODT circuit generates a power voltage for the memory device in response to the setting signal, wherein a voltage level of the power voltage corresponds to the voltage level of the voltage setting command.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.

Abstract: A boost converter is provided. A first terminal of a first inductor of the boost converter is connected to a positive terminal of an input power source. In the of the boost converter, a second terminal of the first inductor is connected to a first terminal of a resonant inductor, and a second terminal of the resonant inductor is connected to a first terminal of a main switch. A second terminal of the main switch is connected to a negative terminal of the input power source. In the of the boost converter, a first terminal of a clamp switch is connected to the second terminal of the resonant inductor, a second terminal of the clamp switch is connected to a first terminal of a first storage capacitor, and a second terminal of the first storage capacitor is connected to the first terminal of the first inductor.

Abstract: A force sensing apparatus with bridge portion comprises a first case, a second case, and a force sensing module. The first case comprises a first annular portion, a first bridge portion, and an inner wall portion. The first bridge portion is connected to an outer periphery of the first annular portion. The inner wall portion is connected to an inner periphery of the first annular portion. The second case comprises a second annular portion, a second bridge portion, and an outer wall portion. The second bridge portion is connected to an inner periphery of the second annular portion. The outer wall portion is connected to an outer periphery of the second annular portion. A stiffness of the second annular portion along an axial direction is greater than a stiffness of the second bridge portion along the axial direction. The second case is disposed on the first case along the axial direction to form a space. The force sensing module is disposed in the space.

Abstract: An IC for adaptive PUF stabilization process includes a PUF stabilizer and a non-volatile memory. The PUF stabilizer has PUF units, a statistic processor, a majority voting generator, and a dark-bit masker. The statistic processor is connected to the PUF units, and performs measurements on the PUF units to output results. The majority voting generator is connected to the statistic processor to accumulate the results into a statistic result, which is output as a PUF bit. The dark-bit masker is connected to the PUF units, and marks unstable PUF units bit as dark-bit and create dark-bit masks. The non-volatile memory is connected to the PUF stabilizer to store the dark-bit masks, and the dark-bits are replaced by specific bit sequences provided by the PUF stabilizer. This decreases bit error rates of the PUF measurement results, and allows customization of the quantity of dark bits per dark-bit mask used.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A light source module includes a light source and a light guide plate. The light guide plate has a light entrance surface, a light exit surface, and a bottom surface. The light entrance surface faces the light source and is located between the light exit surface and the bottom surface. The bottom surface is opposite to the light exit surface and has a plurality of microstructures. The microstructures are a plurality of ridge-shaped microstructures formed in the light guide plate. Each of the microstructures includes a light-facing surface, and a first included angle between the light-facing surface and the bottom surface is 30 degrees to 70 degrees.

Abstract: Semiconductor devices including the use of solder materials and methods of manufacturing are provided. In embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. By utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.

Abstract: The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.