Abstract: A compound is provided as having a structure of Formula I: where X1 and X2 are each independently a nitrogen atom or a C—R group, C is a carbon atom, R is a hydrogen atom, a deuterium atom, a halogen atom, or a cyano group, CR, and at least one of X1 and X2 is N; L1, L2, and L3 are each independently a single bond, a substituted or unsubstituted aryl group, or substituted or unsubstituted aryl heteroaryl group; and Ar1, Ar2 are each independently a substituted or unsubstituted aryl group or a substituted or unsubstituted heteroaryl group.

Abstract: A compound is provided as having the structure of Formula I, where: A and B are each independently a substituted or unsubstituted aryl group or a substituted or unsubstituted heteroaryl group; L1, L2 are each independently a single bond, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heteroaryl group; Ar1, Ar2, Ar3, and Ar4 are each independently a hydrogen atom, a deuterium atom, a cyano group, a nitro group, an amino group, a hydroxy group, a halogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heteroaryl group.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, the three-dimensional memory device including: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer; wherein an outer sidewall of the second channel layer is in contact with an inner sidewall of the first channel layer.

Abstract: The present disclosure provides a three-dimensional memory comprising: a storage channel structure vertically penetrating a plurality of stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising: a block layer in contact with the select gate structure, an insulating layer covering the block layer, and a second channel layer in contact with the insulating layer and the first channel layer.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers and comprising a conductive layer sandwiched between two dielectric layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure of alternating insulating layers and word line layers, a first top select gate (TSG) layer over the stack structure, and a separation structure extending through the first TSG layer, where the first TSG layer is divided by the separation structure into a first sub TSG layer and a second sub TSG layer. The semiconductor device includes a conductive layer positioned between the first sub TSG layer and the separation structure, and between the second sub TSG layer and the separation structure.

Abstract: A three-dimensional (3D) memory device includes a memory stack including conductive layers and dielectric layers interleaving the conductive layers, and a channel structure extending through the memory stack along a vertical direction. The channel structure has a plurality of protruding portions protruding along a lateral direction and facing the conductive layers, respectively, and a plurality of normal portions facing the dielectric layers, respectively, without protruding along the lateral direction. The channel structure includes a plurality of blocking structures in the protruding portions, respectively, and a plurality of storage structures in the protruding portions and over the plurality of blocking structures, respectively. A vertical dimension of each of the blocking structures is nominally the same as a vertical dimension of a respective one of the storage structures over the blocking structure.

Abstract: A first opening extending vertically through a dielectric stack is formed above a substrate. The dielectric stack includes vertically interleaved dielectric layers and sacrificial layers. Parts of the sacrificial layers facing the opening are removed to form a plurality of first recesses. A plurality of stop structures are formed along sidewalls of the plurality of first recesses. A plurality of storage structures are formed over the plurality of stop structures in the plurality of first recesses. The plurality of sacrificial layers are removed to expose the plurality of stop structures from a plurality of second recesses opposing the plurality of first recesses. The plurality of stop structures are removed to expose the plurality of storage structures. A plurality of blocking structures are formed over the plurality of storage structures in the plurality of second recesses.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels each disposed over part of the continuous tunneling layer at a respective apex of the plum blossom shape are formed.

Abstract: A liquid metal (LM) dispensing apparatus and method for design and fabrication thereof. Components of the LM dispensing apparatus are designed and tooled based on a target pinout (e.g., a number of, arrangement of, and dimensions of, holes in a substrate to have LM injected therein) and desired LM material. Embodiments employ detachably attached needles using a locking means to provide leak-free interchangeability of the needles. The flexibility with needles makes replacing damaged needles more perfunctory. Embodiments contour the LM reservoir to enhance uniform LM flow to the needles and dispense or inject LM from multiple detachably attached needles concurrently.

Abstract: In one embodiment, a direct injection device includes a head, a plunger, a reservoir, and multiple needles. The head controls extrusion of liquid stored in the reservoir of the direct injection device. For example, the head causes the plunger to compress the liquid in the reservoir, which causes the liquid to be extruded through the needles.

Abstract: Provided herein is technology relating to roadway design and traffic control systems and methods for connected and automated vehicle and highway (CAVH) systems, and particularly, but not exclusively, to systems and methods for controlling switching of vehicles between automated mode and human-driven mode, systems and methods for vehicle merging, diverging, and overtaking on automated lanes of multiple lane highways, systems and methods for emergency management and roadside assistance on automated lanes, and/or systems and methods for managing automated vehicle lanes on urban major and minor expressways.

Abstract: A method for forming a 3D memory device is provided. The method comprises forming a sacrificial layer on a substrate, forming an alternating dielectric stack on the sacrificial layer, forming a plurality of channel holes vertically penetrating the alternating dielectric stack and the sacrificial layer, and forming a first channel layer in each channel hole. The method further comprises forming a second channel layer on the first channel layer in each channel hole, such that a merging point of the second channel layer is higher than a bottom surface of the alternating dielectric stack. The method further comprises removing the sacrificial layer to form a horizontal trench, and forming a selective epitaxial growth layer in the horizontal trench.

Abstract: A method for forming a three-dimensional memory device includes forming an alternating dielectric stack on a substrate and forming an opening extending partially through the alternating dielectric stack. The opening exposes sidewalls of the alternating dielectric stack. The method also includes disposing a protection layer in the opening and on the exposed sidewalls of the alternating dielectric stack. The method further includes extending the opening through the alternating dielectric stack and forming channel layers in the extended opening.

Abstract: A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.

Abstract: A hollow spherical cerium dioxide nanomaterial, preparation method and application thereof; wherein the preparation method uses glucose as a carbon source, urea as a precipitant, cerium trichloride as a cerium source, and water as a solvent to prepare a cerium dioxide/carbon composite material by a hydrothermal method, and then, a hollow spherical cerium dioxide nanomaterial with a multi-shell layer structure is obtained by calcination in a muffle furnace. By adjusting the amount of urea and the calcination temperature, a number of shell layers of the material can be adjusted. Moreover, in the nanomaterial, the number of shell layers can be adjusted, large spacing exists between shell layers, specific surface area can be increased, wherein contact area of the material with an electrolyte increases, but also structural collapse caused by a volume expansion of an electrode material during charging and discharging can be alleviated, and the electrochemical performance is effectively improved.

Abstract: The three-dimensional memory includes a stack structure which includes: a first stack and a second stack, the first stack including control gate layers and first dielectric layers which are stacked alternately, the second stack including top select gate layers and second dielectric layers which are stacked alternately in the same stacking direction; a plurality of channel structures which run though the stack structure and include charge storage layers, the charge storage layers including a plurality of charge storage portions disposed discontinuously in the stacking direction, the charge storage portions being disposed between the adjacent first dielectric layers; and at least one isolation structure which runs through the top select gate layers and is located between the adjacent channel structures.

Abstract: A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.

Abstract: A method for controlling a regenerated chip, a regenerated chip, and a regenerated ink cartridge are provided. The regenerated chip is electrically connected to a printer by means of a first data signal wire and a logic signal wire, and is electrically connected to an ink cartridge chip by means of a second data signal wire. The method for controlling a regenerated chip includes: detecting an operation command sent by the printer by means of the first data signal wire and the logic signal wire; and when it is detected that the operation command is not a selected operation command, sending a data signal to the ink cartridge chip by means of the second data signal wire, wherein the data signal instructs the ink cartridge chip to communicate with the printer.