Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. A glass/ceramic handling layer is then formed on the PV cell structures. The PV cell structures with handling layers are then exfoliated from the mother wafer. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels. The glass/ceramic handling layers provide structural integrity to the thin epitaxial solar cells during the separation process and subsequent handling.

Abstract: A flat panel display substrate (FPDS) testing system configured such that prior to testing, the FPDS is loaded into a pallet to prevent breakage, and to provide electrical connections to test pads on the FPDS. The system achieves high throughput by testing FPDSs using one or more charged particle beams simultaneously with the following operations: unloading of already-tested substrates, loading of substrates ready for testing, assembly of pallets, and alignment of electrical contactors to a large number of FPDS test pads. The system design eliminates a prior art X-Y stage, and all moving electrical connections to the FPDS during testing, reducing costs and improving reliability. In one embodiment, the FPDS testing system has three subsystems: a process chamber, loadlock assembly, and pallet elevator; in another embodiment, the functions of loadlock and pallet elevator are combined to reduce system footprint.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein each of a plurality of silicon donor wafers has a separation layer formed on its upper surface, e.g., porous anodically etched silicon. On each donor wafer, a PV cell is then partially completed including at least part of inter-cell interconnect, after which plural donor wafers are laminated to a backside substrate or frontside. All of the donor wafers are then separated from the partially completed PV cells in an exfoliation process, followed by simultaneous completion of the remaining PV cell structures on PV cells. Finally, a second lamination to a frontside glass or a backside panel completes the PV cell panel. The separated donor wafers may be reused in forming other PV cells. Use of epitaxial deposition to form the layers of the PV cells enables improved dopant distributions and sharper junction profiles for improved PV cell efficiency.

Abstract: An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart to minimize the process volume. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. Purge gases flow outside the wafer sleeve within a reactor chamber to minimize deposition on the walls of the chamber. In addition, sequencing of the illumination of the individual lamps in the lamp module may further improve the linearity of variation in deposition rates within the wafer sleeve. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration. Combining lamp sequencing with cross-flow processing in a multiple reactor system enables high throughput deposition with good film uniformities and efficient use of process gases.

Abstract: An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart to minimize the process volume. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. Purge gases flow outside the wafer sleeve within a reactor chamber to minimize wall deposition. In addition, sequencing of the illumination of the individual lamps in the lamp module may further improve the linearity of variation in deposition rates within the wafer sleeve. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration. Combining lamp sequencing with cross-flow processing in a multiple reactor system enables high throughput deposition with good film uniformities and efficient use of process gases.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.

Abstract: A plasma fluorine resistant polycrystalline alumina ceramic material is produced by forming a green body including alumina and a binder, and sintering the green body for a time from about 8 to 12 hours. The area % of unsintered particles in the polycrystalline alumina ceramic material does not exceed 0.1 area %, resulting in reduced emission of particles from the material after exposure to plasma fluorine.

Abstract: A hydrogen-containing chemical species is included in the reactant gas mixture in a plasma-enhanced CVD process for forming a carbon-containing dielectric film. The CVD reactant gas mixture contains silicon, oxygen, hydrogen and carbon atoms for forming a novel carbon-containing silicon oxide film in which both Si—C and Si—H bonds are present. Because dielectric material deposited in accordance with the invention has a significant number of Si—H bonds, which are more robust than Si—C bonds, it is more resistant to undesired etching and other physical changes during fabrication than dielectric material formed by conventional methods. A method in accordance with the invention allows a faster deposition rate. A dielectric film formed in accordance with the invention has enhanced uniformity characteristics and a dielectric constant less than 3.

Abstract: A dual wafer processing apparatus (4) includes a chamber housing (14) defining an interior and having upper, lower and central portions (18, 20, 16). An electrostatic chuck (34) has electrostatic chucking surfaces (38, 40) on opposite sides. The chuck is rotatably mounted within the chamber housing so that the chucking surfaces face the upper and lower portions of the chamber housing. After a wafer (36) is positioned on a chucking surface, electrostatic forces are used to maintain the wafer secured to the chucking surface. The chuck is then rotated 180.degree. to permit placement of a second wafer on the second chucking surface. Processing of the two wafers occurs simultaneously. Electrostatic chucking surfaces could be replaced by mechanical wafer clamps.

Abstract: A polycrystalline alumina ceramic material which is resistant to a fluorine-comprising plasma is produced by forming a green body including alumina and a binder, and sintering the green body at a temperature ranging from about 1400.degree. C. to about 1700.degree. C. for a time from about 8 to about 12 hours. The area % of unsintered particles in the polycrystalline alumina ceramic material does not exceed 0.1 area %, resulting in reduced emission of particles from the material after exposure to plasma fluorine.

Abstract: A method (100) of cleaning residues from a chemical vapor deposition apparatus (10) is provided. The present method (100) includes introducing into a chamber (12) cleaning gases such as N.sub.2, C.sub.2 F.sub.6, and O.sub.2, and forming a plasma from the cleaning gases. The present method also includes removing residues from interior surfaces of the chamber 12 by forming a volatile product from the residues and at least one of the cleaning gases.

Abstract: A method and apparatus for monitoring a parameter of the RF power applied to a plasma-enhanced chemical vapor deposition (PECVD) chamber. The parameter is used to monitor an aspect of the chamber or a process in the chamber. In particular, the parameter can be used to determine whether the susceptor is properly aligned, determine the spacing of the susceptor from the gas discharge head, determine whether the wafer is properly aligned on the susceptor, determine whether there has been any deterioration of the susceptor or the gas discharge head, and determine whether a chamber clean operation is complete.

Abstract: An improved sandwich layer of silicon dioxide layers for gap filling between metal lines. This is accomplished using a first layer formed in a PECVD process using TEOS and a fluorine-containing compound to give a barrier layer with a dielectric constant of less than 4.0, preferably approximately 3.5. Subsequently, an SACVD process is used with TEOS to form a gap filling layer. By appropriately choosing the thickness of the respective layers, one can adjust the dielectric to a value which is a combination of the dielectric constants of the two different layers, preferably giving a dielectric constant of approximately 3.6-3.7.

Abstract: A method of fabricating a self-aligned gated electron field emitter. An oxidation process forms an optimized, atomically sharp needle (18) in a silicon substrate (12). The needle and surrounding planar area are conformally coated with silicon dioxide (22). A dielectric layer (24) is deposited and planarized over the needle. The dielectric layer is then partially etched away so as to expose the coated needle. The silicon dioxide exposed on the needle is isotropically etched so as to undercut the dielectric layer. A gate metal is directionally deposited so as to form a gate layer (26) on the planar portions of the dielectric layer that is electrically isolated from the gate metal (28) deposited on the needle. The metal on the needle is anodically etched by applying the potential only to the silicon and not to the gate layer. Electro-plating may recoat the needle with another metal (30).

Abstract: Tapered silicon structures, of interest for use, e.g., in atomic force microscopes, in field-emission devices, and in solid-state devices are made using silicon processing technology. Resulting tapered structures have, at their tip, a radius of curvature of 10 nanometers or less.

Abstract: In a structure comprising an ultra-sharp silicon tip coated with a layer of material, the silicon is removed from the structure. The remaining material is utilized as a mold. Metal deposited in the mold replicates the original silicone tip. In this way, ultra-sharp all-metal tips suitable, for example, as field-emitter sources are provided.