Patents by Inventor Toan Duc Pham
Toan Duc Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9508408Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: GrantFiled: April 2, 2014Date of Patent: November 29, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Ming-Ju Edward Lee, Shadi M. Barakat, Warren Fritz Kruger, Xiaoling Xu, Toan Duc Pham, Aaron John Nygren
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Patent number: 8862966Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: GrantFiled: July 30, 2010Date of Patent: October 14, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Publication number: 20140211571Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: ApplicationFiled: April 2, 2014Publication date: July 31, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Ming-Ju Edward LEE, Shadi M. BARAKAT, Warren Fritz KRUGER, Xiaoling XU, Toan Duc PHAM, Aaron John NYGREN
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Patent number: 8730758Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: GrantFiled: June 24, 2009Date of Patent: May 20, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ju Edward Lee, Shadi M. Barakat, Warren Fritz Kruger, Xiaoling Xu, Toan Duc Pham, Aaron John Nygren
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Patent number: 8671304Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: GrantFiled: July 30, 2010Date of Patent: March 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Patent number: 8489912Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.Type: GrantFiled: July 30, 2010Date of Patent: July 16, 2013Assignee: ATI Technologies ULCInventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael John Litt
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Patent number: 8443225Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: August 13, 2012Date of Patent: May 14, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Publication number: 20120303995Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: ApplicationFiled: August 13, 2012Publication date: November 29, 2012Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 8245073Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: July 24, 2009Date of Patent: August 14, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Publication number: 20110208989Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.Type: ApplicationFiled: July 30, 2010Publication date: August 25, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael John Litt
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Publication number: 20110185256Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: ApplicationFiled: July 30, 2010Publication date: July 28, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Publication number: 20110185218Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: ApplicationFiled: July 30, 2010Publication date: July 28, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Publication number: 20110019787Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Inventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Publication number: 20100329045Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: ApplicationFiled: June 24, 2009Publication date: December 30, 2010Applicant: Advanced Micro Devices, Inc.Inventors: Ming-Ju Edward LEE, Shadi M. Barakat, Warren Fritz Kruger, Xiaoling Xu, Toan Duc Pham, Aaron John Nygren