Abstract: A technique for selecting context models (CMs) for a CM ensemble (CME) in a context mixing compressor includes measuring compression ratios (CRs) of the compressor on a dataset for each CM included in a base set of CMs. A first CM that has a maximum CR for the dataset is added to the CME. In response to a desired number of the CMs not being in the CME, subsequent CRs for the compressor are measured on the dataset for each of the CMs in the base set of CMs that are not in the CME in conjunction with one or more CMs in the CME. In response to a desired number of the CMs not being in the CME, subsequent CMs that in conjunction with the one or more CMs in the CME result in a maximum subsequent CR for the dataset are added to the CME.

Abstract: In a data storage system, a prior set S of prefix codes for pseudo-dynamic compression as well as data compressed utilizing prior set S are stored. While data compressed utilizing prior set S are stored in the data storage system, the number of prefix codes utilized by the data storage system for pseudo-dynamic compression are augmented. Augmenting the number of codes includes determining a new set S? of prefix codes for pseudo-dynamic compression from a training data set selected from a workload of the data storage system and storing the new set S? in the data storage system with the prior set S.

Abstract: Symbols are loaded into a diagonal anti-diagonal structure. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol are positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

Abstract: A decoder performs iterative decoding of a codeword encoded by a binary symmetry-invariant product code, such as a half product code or quarter product code. In response to the iterative decoding reaching a stopping set, the decoder determines by reference to an ambient error graph formed from the stopping set whether or not the stopping set is correctable by post-processing. If not, the decoder outputs the uncorrected codeword and signals a decoding failure. In response to determining that the stopping set is correctable by post-processing, the decoder inverts all bits of the codeword corresponding to edges of the ambient error graph, applies an additional round of iterative decoding to the codeword to obtain a corrected codeword, and outputs the corrected codeword. Post-processing in this manner substantially lowers an error floor associated with the binary symmetry-invariant product code.

Abstract: In at least one embodiment, a history data structure of a Lempel-Ziv compressor is preloaded with fixed predetermined history data typical of actual data of a workload of the Lempel-Ziv compressor. The Lempel-Ziv compressor then compresses each of multiple data pages in a sequence of data pages by reference to the fixed predetermined history data.

Abstract: Symbols are loaded into a diagonal anti-diagonal structure. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol are positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

Abstract: A technique for selecting context models (CMs) for a CM ensemble (CME) in a context mixing compressor includes measuring compression ratios (CRs) of the compressor on a dataset for each CM included in a base set of CMs. A first CM that has a maximum CR for the dataset is added to the CME. In response to a desired number of the CMs not being in the CME, subsequent CRs for the compressor are measured on the dataset for each of the CMs in the base set of CMs that are not in the CME in conjunction with one or more CMs in the CME. In response to a desired number of the CMs not being in the CME, subsequent CMs that in conjunction with the one or more CMs in the CME result in a maximum subsequent CR for the dataset are added to the CME.

Abstract: A multi-chip device and method for storing input data. The multi-chip device includes: a plurality of memory chips being adapted to store encoded input data, wherein each of the plurality of memory chips includes a detection unit that outputs detection information; an evaluation unit being adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit being adapted to receive the detected bits and to combine the detected bits; and a decoding unit being adapted to output decoded data by decoding the combined detected bits. The present invention also provides a method and a computer program product for storing input data.

Abstract: A decoder performs iterative decoding of a codeword encoded by a binary symmetry-invariant product code, such as a half product code or quarter product code. In response to the iterative decoding reaching a stopping set, the decoder determines by reference to an ambient error graph formed from the stopping set whether or not the stopping set is correctable by post-processing. If not, the decoder outputs the uncorrected codeword and signals a decoding failure. In response to determining that the stopping set is correctable by post-processing, the decoder inverts all bits of the codeword corresponding to edges of the ambient error graph, applies an additional round of iterative decoding to the codeword to obtain a corrected codeword, and outputs the corrected codeword. Post-processing in this manner substantially lowers an error floor associated with the binary symmetry-invariant product code.

Abstract: A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.

Abstract: In at least one embodiment, a history data structure of a Lempel-Ziv compressor is preloaded with fixed predetermined history data typical of actual data of a workload of the Lempel-Ziv compressor. The Lempel-Ziv compressor then compresses each of multiple data pages in a sequence of data pages by reference to the fixed predetermined history data.

Abstract: A mechanism is provided for high-throughput compression of data. Responsive to receiving an indication of a match of a current 4-byte sequence from an incoming data stream to stored hash values in a set of hash tables, numerous variables are set to initial values. Responsive to receiving a subsequent 4-byte sequence from the incoming data stream and determining that an active match variable is set to one, the subsequent 4-byte sequence is compared to data in a copy of the incoming data stream in memory at an active position with a predefined length offset. A constraint variable is set to a number of bytes for which the match is to be extended. Responsive to the constraint variable being below a predetermined number, a length, distance pair is output indicating a match to a previous pattern in the incoming data stream.

Abstract: In a data storage system, a prior set S of prefix codes for pseudo-dynamic compression as well as data compressed utilizing prior set S are stored. While data compressed utilizing prior set S are stored in the data storage system, the number of prefix codes utilized by the data storage system for pseudo-dynamic compression are augmented. Augmenting the number of codes includes determining a new set S? of prefix codes for pseudo-dynamic compression from a training data set selected from a workload of the data storage system and storing the new set S? in the data storage system with the prior set S.

Abstract: A mechanism is provided for high-throughput compression of data. Responsive to receiving an indication of a match of a current 4-byte sequence from an incoming data stream to stored hash values in a set of hash tables, numerous variables are set to initial values. Responsive to receiving a subsequent 4-byte sequence from the incoming data stream and determining that an active match variable is set to one, the subsequent 4-byte sequence is compared to data in a copy of the incoming data stream in memory at an active position with a predefined length offset. A constraint variable is set to a number of bytes for which the match is to be extended. Responsive to the constraint variable being below a predetermined number, a length, distance pair is output indicating a match to a previous pattern in the incoming data stream.

Abstract: A multidimensional storage array (SA) system includes storage elements (SEs) arranged in storage array partitions, a plurality of input shifters, and a plurality of output shifters. One respective input shifter and output shifter is associated with one partition. The SEs are arranged into rows and columns and each store particular bit(s) of a data word. Each of the input shifters implements a positional shift to a data word that is then loaded to the associated partition. Each of the output shifters unloads a loaded data word, reverses the positional shift of the unloaded data word, and provides the data word to a requesting device, such as a decoder. The loaded data words are exposed so that multiple row or column addressed data words may be unloaded from the SA simultaneously in a single clock cycle. Multiple column or row address data word segments may be physically diagonally arranged within each storage array partition.

Abstract: A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.

Abstract: A method and a device for removing pathologic error patterns in binary data are proposed. The method comprises the operations of identifying a pathologic error pattern in the binary data, and inverting all bits of the identified pathologic error pattern.