Abstract: A method for operating a memory device comprising at least one memory unit. The at least one memory unit includes a bistable multivibrator and two access transistors for the controllable connection of the bistable multivibrator to two secondary control lines associated with the at least one memory unit. The connection of the bistable multivibrator to the two secondary control lines can be controlled using a first primary control line. The method includes: applying a control signal to a control terminal of at least one of the two access transistors in such a way that a load path of the at least one access transistor is at least partially electrically conductive, with respect to a high-resistance state of the load path of the at least one access transistor; determining a first variable which characterizes at least one current flowing through the load path of the at least one access transistor.

Abstract: An apparatus. The apparatus includes at least a first comparator device, which is designed to compare a first input current with a first reference current and, based on the comparison, to output a first output current to a second comparator device, wherein the first output current corresponds to a difference of the first reference current and the first input current if the first input current is smaller than the first reference current, and wherein the first output current corresponds to a difference of the first input current and the first reference current if the first input current is greater than or equal to the first reference current.

Abstract: A scalar product circuit for computing a binary scalar product of an input vector and a weight vector. The scalar product circuit includes one or multiple adders and at least one matrix circuit including memory cells that are arranged in multiple rows and multiple columns in the form of a matrix, each memory cell including a first memory state and a second memory state. Each matrix circuit includes at least one weight range including one or multiple bit sections, the matrix circuit including an analog-to-digital converter and a bit shifting unit connected thereto for each bit section, the column lines of the bit section being connected to the analog-to-digital converter, and a column selection switching element being provided for each column. The bit shifting units are connected to one of the adders, those bit shifting units that are included in a weight range being connected to the same adder.

Abstract: A device including a first comparator unit, the first comparator unit including a first reference current provision unit for providing a first reference current and a first comparison current provision unit for providing a first comparison current, and the first comparator unit being designed to compare the first reference current with the first comparison current in order to obtain a first comparison result and, based on the first comparison result, to influence at least one reference current and/or at least one comparison current of at least one further comparator unit.

Abstract: A processor for performing a predetermined computational operation in which one or multiple data element(s) is/are used to determine a result. The processor includes one or more processor core(s) and at least one buffer memory, connectable to a main memory, and if the main memory is connected, it is designed to access the main memory. Each processor core is designed to execute instructions. The at least one buffer memory includes a calculation circuit which is designed to perform the computational operation in response to an execution signal if the one or the multiple data element(s) is/are stored in the buffer memory, the result being stored in the buffer memory. The processor is designed to perform the computational operation optionally using one of the processor cores with the aid of the instructions or to perform it in the at least one buffer memory using the respective calculation circuit.

Abstract: A method for executing one or multiple vector matrix operations using a matrix operation circuit. The method includes: receiving an input vector having a plurality of input values; applying and increasing row voltages on row lines of the matrix, wherein the row voltages are increased linearly starting from zero, and for each of the row voltages, a rate of increase is proportional to one of the input values; detecting the output currents generated at the current outputs; comparing current intensities of the detected output currents to a predetermined limit current intensity; terminating the increase of the row voltages, if, upon comparison, it is established that at least one of the output currents has a current intensity which is greater than the limit current intensity; and determining one or multiple output vectors having a plurality of output values on the basis of the measured currents.

Abstract: An electricity metering circuit for a matrix operation circuit, having a circuit input for an electrical input current that is an output current of the matrix operation circuit. The electricity metering circuit is set up to provide a ground potential at the circuit input, to integrate the input current at the circuit input over time, to store a storage charge that is increased up to a predetermined maximum storage charge in accordance with a proportionality constant, proportionally to the integrated input current, to quantify the integrated input current in a charge unit, the charge unit corresponding to the maximum storage charge taking into account the proportionality constant, and to determine the integrated input current rounded down to the nearest integer charge unit as a count sum.

Abstract: An apparatus including a first comparator device. The first comparator device includes a first reference current providing device for providing a first reference current and a first comparison current providing device for providing a first comparison current. The first comparator device is configured to compare the first reference current with the first comparison current to obtain a first comparison result and output a first output signal characterizing the first comparison result based on the first comparison result.

Abstract: An actuating unit, for a memory that includes at least one memory cell in which one of a plurality of discrete storable values is encodable as an electrical resistance value of a memristor, includes: a measuring device configured to measure the resistance value of the memristor; a discretizer configured to allocate to the measured resistance value one of the plurality of discrete storable values as the read value; a comparator unit configured to ascertain the difference between the nominal resistance value of the memristor that corresponds to the read value and the measured resistance value of the memristor; and a driver configured to apply, to the memristor on the basis of the ascertained difference, a current-time profile that drives the actual resistance value of the memristor in the direction of the nominal resistance value that corresponds to the read value, so that the memory cell is refreshed.

Abstract: A circuit includes a rectifier, e.g., including four diodes; a semiconductor switch; a coil that is chargeable, is dischargeable, and has (a) a first terminal connected to a first output terminal of the rectifier and (b) a second terminal connected via the semiconductor switch to a second output terminal of the rectifier; a first resistor via which a control terminal of the semiconductor switch is connected to the first output terminal of the rectifier; a second resistor connected between the second output terminal of the rectifier and the control terminal of the semiconductor switch; and a discharge unit connected between the second terminal of the coil and the control terminal of the semiconductor switch. The charging and discharging is implemented by, respectively, connecting both of, and disconnecting one or both of, first and second input terminals of the rectifier to/from the voltage source.

Abstract: A method for implementing a matrix operation. A first digital result is determined for the matrix operation as a function of a first analog addition using a first memristor array, a second digital result being determined as a function of a second analog addition using a second memristor array, and the first result and the second result being digitally added. A device for implementing a matrix operation. The device includes at least one first memristor array and one second memristor array, a first analog-to-digital converter and a second analog-to-digital converter. The device is designed to determine a first digital result for the matrix operation as a function of a first analog addition using the first memristor array and of the first analog-to-digital converter, and to determine a second digital result as a function of a second analog addition using the second memristor array and of the second analog-to-digital converter.

Abstract: An image sensor element for outputting an image signal. The image sensor element initially includes a first photoelement, the first photoelement being situated on a spatial area of a pixel on a semiconductor substrate. The image sensor element also includes a second photoelement that is doped and/or provided with a color filter in such a way that a spectral sensitivity of the first photoelement differs from a spectral sensitivity of the second photoelement. Lastly, the image sensor element includes an evaluation electronics system that is situated in the area of the pixel on the semiconductor substrate, the evaluation electronics system being situated in the area of the pixel in which the first photoelement is also implemented. The evaluation electronics system is designed to process a photoelement signal of the first photoelement and a photoelement signal of the second photoelement to form the image signal.

Abstract: A circuit includes a rectifier, e.g., including four diodes; a semiconductor switch; a coil that is chargeable, is dischargeable, and has (a) a first terminal connected to a first output terminal of the rectifier and (b) a second terminal connected via the semiconductor switch to a second output terminal of the rectifier; a first resistor via which a control terminal of the semiconductor switch is connected to the first output terminal of the rectifier; a second resistor connected between the second output terminal of the rectifier and the control terminal of the semiconductor switch; and a discharge unit connected between the second terminal of the coil and the control terminal of the semiconductor switch. The charging and discharging is implemented by, respectively, connecting both of, and disconnecting one or both of, first and second input terminals of the rectifier to/from the voltage source.

Abstract: An image sensor element for outputting an image signal. The image sensor element initially includes a first photoelement, the first photoelement being situated on a spatial area of a pixel on a semiconductor substrate. The image sensor element also includes a second photoelement that is doped and/or provided with a color filter in such a way that a spectral sensitivity of the first photoelement differs from a spectral sensitivity of the second photoelement. Lastly, the image sensor element includes an evaluation electronics system that is situated in the area of the pixel on the semiconductor substrate, the evaluation electronics system being situated in the area of the pixel in which the first photoelement is also implemented. The evaluation electronics system is designed to process a photoelement signal of the first photoelement and a photoelement signal of the second photoelement to form the image signal.

Abstract: An actuating unit, for a memory that includes at least one memory cell in which one of a plurality of discrete storable values is encodable as an electrical resistance value of a memristor, includes: a measuring device configured to measure the resistance value of the memristor; a discretizer configured to allocate to the measured resistance value one of the plurality of discrete storable values as the read value; a comparator unit configured to ascertain the difference between the nominal resistance value of the memristor that corresponds to the read value and the measured resistance value of the memristor; and a driver configured to apply, to the memristor on the basis of the ascertained difference, a current-time profile that drives the actual resistance value of the memristor in the direction of the nominal resistance value that corresponds to the read value, so that the memory cell is refreshed.

Abstract: A method for operating a data processing unit of a driver assistance system, the unit including main and slave computers. The main computer ascertains surroundings data from a surroundings detection system by using a processing specification. The slave computer operates a communication interface of the data processing unit, using a communication instruction. The method includes initializing, a first testing, a carrying out, a second testing and a forwarding. In initializing, the main computer, in response to a signal, is initialized by performing an initialization instruction on the main computer. In the first testing, the slave computer, in response to the signal, is initialized by performing a self-test instruction on the slave computer. In the carrying out, the communication instruction is performed on the slave computer to send and/or receive data via the communication interface, when the slave computer is tested and while the main computer is initialized.

Abstract: A method for operating a data processing unit of a driver assistance system, the unit including main and slave computers. The main computer ascertains surroundings data from a surroundings detection system by using a processing specification. The slave computer operates a communication interface of the data processing unit, using a communication instruction. The method includes initializing, a first testing, a carrying out, a second testing and a forwarding. In initializing, the main computer, in response to a signal, is initialized by performing an initialization instruction on the main computer. In the first testing, the slave computer, in response to the signal, is initialized by performing a self-test instruction on the slave computer. In the carrying out, the communication instruction is performed on the slave computer to send and/or receive data via the communication interface, when the slave computer is tested and while the main computer is initialized.

Abstract: The invention relates to a control valve having a valve seat and a valve disk (1), which can be moved from a closed position, in which the valve disk (1) rests on the valve seat and the relief valve is closed, into a through-flow position, in which the relief valve is open, wherein the valve disk (1) comprises a valve disk surface (2) having a peripheral surface rim (4) and a normal which is perpendicular to the valve disk surface (2), runs through the center of gravity of the latter and defines a longitudinal axis L. A brim is arranged on the surface rim (4), wherein said brim has a first part (6) which projects beyond the valve disk surface (2) in the axial direction with respect to the longitudinal axis L and has a second part (8) which adjoins the first part (6) and comprises a section that is radial with respect to the longitudinal axis L.

Abstract: A method for acoustically sensing an area is described. An acoustic transmit pulse is transmitted into the area by an acoustic transducer and a received signal is acquired with the aid of the transducer, in order to receive the transmit pulse reflected back from the area. Within a post-pulse oscillation time of the transducer, which directly follows the emission of the transmit pulse, the actual phase response of the received signal is determined. In the event the actual phase response deviates from a predefined setpoint phase response, an object is detected within the area. Also described is a device for acoustically sensing an area, which is designed to carry out the method.

Abstract: A method and a control unit for controlling the authorization of charging operations of electrically operated vehicles. A control unit is provided between a main terminal and a plurality of electric coupler sockets, which are connected to the control unit via a power line. A vehicle to be charged is connected to one of the electric coupler sockets, and the total charging current, which is conducted from the main terminal to the electric coupler sockets via the control unit, is measured. Charging-current requests are transmitted to the control unit by each of the vehicles connected to the electric coupler sockets, and the total charging current is compared to the sum of the charging currents reported by the vehicles connected to the charging outlets. The charging outlets are switched off if the total charging current exceeds the sum. The connecting of a vehicle to be charged includes transmitting authorization information from the vehicle to the control unit.