Patents by Inventor Tobias Zirr

Tobias Zirr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230297513
    Abstract: A cache streaming apparatus and method for machine learning. For example, one embodiment of an apparatus comprises: a plurality of compute units to perform machine learning operations; a cache subsystem comprising a hierarchy of cache levels, at least some of the cache levels shared by two or more of the plurality of compute units; and data streaming hardware logic to stream machine learning data in and out of the cache subsystem based on the machine learning operations, the data streaming hardware logic to load data into the cache subsystem from memory before the data is needed by a first portion of the machine learning operations and to ensure that results produced by the first portion of machine learning operations are maintained in the cache subsystem until used by a second portion of the machine learning operations.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventors: Prasoonkumar SURTI, Tobias ZIRR, Abhishek R. APPU, Anton KAPLANYAN, Pawel MAJEWSKI, Joshua BARCZAK
  • Publication number: 20230297508
    Abstract: Embodiments of the invention include acceleration hardware for performing texture lookups and for interpolation for textures backed by hashed memory layouts. In particular, on a texel fetch, a special texture addressing mode allows integer texel coordinates to be hashed and combined with dedicated hardware, to arrive at a pseudo-random memory address for each texel within the memory block allocated to back the respective sampled texture.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventors: TOBIAS ZIRR, CARSTEN BENTHIN
  • Publication number: 20230297415
    Abstract: Apparatus and method for scheduling inference tasks. For example, one embodiment of an apparatus comprises: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventors: PAWEL MAJEWSKI, PRASOONKUMAR SURTI, TOBIAS ZIRR
  • Publication number: 20230142467
    Abstract: A graphics processor is provided that includes circuitry configured to generate auxiliary motion vectors for higher-order light-based effects such as shadows, objects reflecting in mirrors, waves in water or other liquids, glossy surfaces, or objects visible through transparent and/or refractive glass. The circuitry is configured to apply light path constraints to simplify the calculations used to generate the auxiliary motion vectors.
    Type: Application
    Filed: September 21, 2022
    Publication date: May 11, 2023
    Applicant: Intel Corporation
    Inventors: Anton Kaplanyan, Tobias Zirr
  • Publication number: 20230147063
    Abstract: A residual network is used to predict a set of residual motion vectors that provide additional motion data for portions of the frame for which motion vectors are not provided, such as animated textures, mirrored/reflected objects, and/or moving objects without motion information.
    Type: Application
    Filed: August 15, 2022
    Publication date: May 11, 2023
    Applicant: Intel Corporation
    Inventors: SungYe Kim, Tobias Zirr
  • Publication number: 20230144562
    Abstract: A graphics processor is provided that includes circuitry configured to facilitate correspondence finding for higher-order light-based effects such as shadows, objects reflecting in mirrors, waves in water or other liquids, glossy surfaces, or objects visible through transparent and/or refractive glass. The circuitry is configured to procedurally generate temporally stable tracking data for transparent and reflective surfaces during rendering of successive frames, hierarchically analyze the successive frames to detect the procedurally generated data within the successive frames, generate residual motion vectors based on the hierarchical analysis, and warp and align a frame and a successively rendered frame based on renderer supplied motion vectors and the residual motion vectors.
    Type: Application
    Filed: September 19, 2022
    Publication date: May 11, 2023
    Applicant: Intel Corporation
    Inventors: Tobias Zirr, Anton Kaplanyan
  • Publication number: 20230146259
    Abstract: Sampling across multiple views in supersampling operation is described. An example of an apparatus includes one or more processing resources configured to perform a supersampling operation for image data generated for multiple views utilizing one or more neural networks, the processing resources including at least a first circuitry to process a first current frame including first image data for a first view, and a second circuitry to process a second current frame including second image data for a second view, the first view and second view being displaced from each other, the processing resources to receive for processing the first current frame and the second current frame, and perform supersampling processing utilizing the one or more neural networks based on at least the first current frame and the second current frame and one or more prior generated frames for each of the views.
    Type: Application
    Filed: November 3, 2022
    Publication date: May 11, 2023
    Applicant: Intel Corporation
    Inventors: Gabor Liktor, Karthik Vaidyanathan, Tobias Zirr
  • Publication number: 20230065183
    Abstract: A graphics processor is provided that includes circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, velocity data, and jitter offset data. The neural network model is configured to generate a denoised, supersampled, and anti-aliased output image based on reliability metrics computed based on sample distribution data for samples within the current frame data.
    Type: Application
    Filed: November 5, 2021
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventors: Tobias Zirr, SungYe Kim