Abstract: A method and apparatus provide an equalization time delay to synchronize a plurality of paging transmitters in a simulcast paging system. A delay equalization circuit (41 ) appropriate for use with an analog input signal includes a coder/decoder (CODEC) (50) and a digital signal processor (DSP) (58). An analog input signal is digitized or sampled by an analog-to-digital converter (ADC) in the CODEC, producing corresponding digital values that are input to the DSP. The DSP employs a selected finite impulse filter to interpolate between the sampled digital values from the CODEC to provide enhanced resolution in delaying a signal output that is output. The DSP determines a major sample index and an interpolated filter index to achieve the desired equalization time delay. These variables define two delay intervals that are combined to provide the required equalization time delay.

Abstract: A digital exciter (30) for selectively modulating digital or analog input data. The digital exciter includes a digital signal modulator (32) and a digital quadrature modulator (DQM)(36) comprising two digital signal processors (DSPs). The signal modulator is controlled by a control (40). An operator can selectively determine whether the digital exciter is used for modulating either two level or four level NRZ digital data and whether the device is to provide linear modulation or frequency modulation (FM) of the input signal. An interpolator (38) interpolates a 662/3 kHz timer interrupt rate used in the signal modulator to a 400 kHz rate, thereby reducing the processing load on the DSP comprising the DQM by simplifying the sine and cosine values used in the quadrature modulation. An operator can select from among a plurality of operating parameters on a menu for controlling the signal modulator, either from a local or a remote video display terminal (VDT).

Abstract: A method and apparatus for compensating fading and interference in a radio signal. A plurality of pilot symbols are appended to a plurality of data symbols to form successive frames that are modulated at a transmitter. The transmitted modulated signal is subject to loss of data due to simple fading and multi-path and simulcast interference. The received signals are demodulated by a receiver and processed to provide a data signal comprising the data symbols and a pilot signal comprising the pilot symbols. The data signal is delayed for sufficient time to enable channel impulse response estimates to be made of successive blocks of pilot symbols, preferably using pilot symbol blocks that both precede and follow the data symbols in the frame being processed.

Abstract: A modem for use in a simulcast paging system includes a modulator (26) and a demodulator (30), both of which produce very low jitter, enabling the modem to be used at data rates well in excess of 1,200 baud. Both the modulator and the demodulator are implemented in software using a digital signal processor (DSP) (66). The modulator initially samples a non-return-to-zero (NRZ) input at a sample rate of 19.2 KHz, interpolates transitions between logic levels, and produces a frequency shift keyed (FSK) modulated signal at a center frequency different than that used for transmitting the modulated signal. Using an interpolation timer that responds to changes in logic level on the input, the modulator changes the frequency of the FSK modulated signal at the appropriate time with much greater accuracy than would be possible without interpolation. The FSK modulated signal is filtered to substantially attenuate frequencies outside a 3 KHz bandwidth, producing a filtered signal.

Abstract: A modem for use in a simulcast paging system includes a modulator (26) and a demodulator (30), both of which produce very low jitter, enabling the modem to be used at data rates well in excess of 1,200 baud. Both the modulator and the demodulator are implemented in software using a digital signal processor (DSP) (66). The modulator initially samples a non-return-to-zero (NRZ) input at a sample rate of 19.2 KHz, interpolates transitions between logic levels, and produces a frequency shift keyed (FSK) modulated signal at a center frequency different than that used for transmitting the modulated signal. Using an interpolation timer that responds to changes in logic level on the input, the modulator changes the frequency of the FSK modulated signal at the appropriate time with much greater accuracy than would be possible without interpolation. The FSK modulated signal is filtered to substantially attenuate frequencies outside a 3 KHz bandwidth, producing a filtered signal.