Patents by Inventor Todd Adelmann

Todd Adelmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070165513
    Abstract: A storage device comprises a probe having a tip. The storage device also comprises a storage medium, with the tip of the probe to form the groove in the storage medium. The probe tip interacts with a surface of the groove to store and read data.
    Type: Application
    Filed: February 6, 2007
    Publication date: July 19, 2007
    Inventor: Todd Adelmann
  • Publication number: 20050185567
    Abstract: A storage device includes a storage medium having plural storage cells, and a probe to scan across a surface of the storage medium to program the storage cells. The probe is adapted to selectively program each storage cell to one of more than two storage states.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 25, 2005
    Inventor: Todd Adelmann
  • Publication number: 20050149687
    Abstract: In accordance with an embodiment of the present invention, a method for identification of a semiconductor device having a plurality of memory blocks, comprises accessing a memory profile for the semiconductor device based at least in part on an identification of defective memory blocks of the semiconductor device and determining a unique identifier for the semiconductor device based at least in part on the memory profile of the semiconductor device.
    Type: Application
    Filed: February 18, 2005
    Publication date: July 7, 2005
    Inventor: Todd Adelmann
  • Publication number: 20050060628
    Abstract: A device comprises a memory array in which a plurality of codewords is stored. Each codeword comprises an error correction code and a data block that comprises a plurality of units of data. The device further comprises an error code correction module coupled to the memory array. When multiple units of data are to be read from the device for an address, a codeword stored in a location associated with the address is fetched from the memory array, the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 17, 2005
    Inventors: Andrew Spencer, Todd Adelmann, Stewart Wyatt, Kenneth Smith
  • Publication number: 20050055621
    Abstract: Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to read error correction coded data from the array of memory cells, provide error correction code decoding to selected error correction coded data and discard unused error correction code parity data of unselected error correction coded data.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 10, 2005
    Inventors: Todd Adelmann, Stewart Wyatt, Kenneth Smith
  • Publication number: 20050036428
    Abstract: A storage device comprises a probe having a tip. The storage device also comprises a storage medium, with the tip of the probe to form the groove in the storage medium. The probe tip interacts with a surface of the groove to store and read data.
    Type: Application
    Filed: August 13, 2003
    Publication date: February 17, 2005
    Inventor: Todd Adelmann
  • Publication number: 20050038950
    Abstract: A storage device comprises a probe and storage cell having moveable parts that are actuatable to plural positions to represent respective different data states. The probe interacts with the moveable parts to selectively actuate the moveable parts to the plural positions.
    Type: Application
    Filed: August 13, 2003
    Publication date: February 17, 2005
    Inventor: Todd Adelmann
  • Publication number: 20050013181
    Abstract: Disclosed herein are assisted memory devices having an integrated cache and methods implemented therein. In one embodiment, an integrated circuit device comprises a memory array integrated on a substrate with a decoder and a cache also integrated on the same substrate. The decoder may be configured to decode data retrieved from the memory array. The cache may be configured to retrieve data stored in the memory array in anticipation of a request for the data.
    Type: Application
    Filed: July 17, 2003
    Publication date: January 20, 2005
    Inventors: Todd Adelmann, Stewart Wyatt
  • Publication number: 20050013230
    Abstract: A storage device includes a storage medium and a probe having plural tips. The storage medium has a surface in which storage cells are to be formed. The tips of the probe form plural perturbations in the surface in at least one of the storage cells for representing a data bit.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 20, 2005
    Inventor: Todd Adelmann
  • Publication number: 20050007815
    Abstract: A memory array for a magneto-resistive memory device is provided. The array includes a plurality of memory cells disposed in rows and columns in the memory array. Each memory cell is paired with another memory cell such that the pair of memory cells are driven to first and second, different states by the same signals. A sense point for reading data from a pair of memory cells is also provided. The sense point is located at a point with one of the memory cells of each pair on one side of the sense point and the other memory cell of each pair located on the other side of the sense point.
    Type: Application
    Filed: July 7, 2003
    Publication date: January 13, 2005
    Inventor: Todd Adelmann