Patents by Inventor Todd Albertson

Todd Albertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11552432
    Abstract: A shield for a cable attachment system for attaching a cable to a component having a ball grid array (BGA). The shield may comprise an outer conductive surface, a first end configured to be coupled to a surface of the component, a second end that receives the cable, and an inner non-conductive material received within the shield adjacent the first end and encasing the connection of the cable to the BGA of the component. The cable may be configured to be coupled to the BGA of the component.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 10, 2023
    Assignee: High Speed Interconnects, LLC
    Inventors: Antonio De La Rosa, Todd Albertson
  • Publication number: 20220313069
    Abstract: A cable assembly, comprising a component, a cable, a rigid adhesive and a flexible adhesive. The cable may be coupled to the component. The rigid adhesive may be applied to cover the connection of the cable to the component. The flexible adhesive may be applied to cover the rigid adhesive. The component may comprise a ball grid array (BGA) and the cable may be coupled to the BGA. A hypodermic tubing may be applied over a portion of the rigid adhesive.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Antonio De La Rosa, Todd Albertson
  • Publication number: 20210153344
    Abstract: A foldable modular flex circuit for attaching to at least one component. The flex circuit may comprise a central area and at least one tab depending from the central area. The central area may comprise a cable attachment section configured to electrically couple to at least one coaxial cable. A first tab may depend from the central area and is configured to electrically couple to a ball grid array (BGA) of the component. A second pair of tabs may depend from the central area and are configured to electrically couple to an additional at least one component, wherein each tab depends substantially perpendicular from the central area.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Inventors: Antonio De La Rosa, Todd Albertson
  • Patent number: 10939545
    Abstract: A foldable modular flex circuit for attaching to at least one component. The flex circuit may comprise a central area and at least one tab depending from the central area. The central area may comprise a cable attachment section configured to electrically couple to at least one coaxial cable. A first tab may depend from the central area and is configured to electrically couple to a ball grid array (BGA) of the component. A second pair of tabs may depend from the central area and are configured to electrically couple to an additional at least one component, wherein each tab depends substantially perpendicular from the central area.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 2, 2021
    Assignee: High Speed Interconnects, LLC
    Inventors: Antonio De La Rosa, Todd Albertson
  • Publication number: 20210052142
    Abstract: A cable attachment system and method for use with micro sensing component in a sterile environment. The cable attachment system may comprise a sensor, a cable connected to the sensor at a first end, a connector coupled to a second end of the cable, and a board coupled to the connector. A medical grade tubing may encase the connection of the sensor to the cable and a medical grade housing may encase the connection of the board to the connector and connected to the tubing. The medical grade housing and tubing are configured to create a sealed internal volume in the sterile environment.
    Type: Application
    Filed: August 23, 2020
    Publication date: February 25, 2021
    Inventors: Antonio De La Rosa, Todd Albertson
  • Publication number: 20210050691
    Abstract: A shield for a cable attachment system for attaching a cable to a component having a ball grid array (BGA). The shield may comprise an outer conductive surface, a first end configured to be coupled to a surface of the component, a second end that receives the cable, and an inner non-conductive material received within the shield adjacent the first end and encasing the connection of the cable to the BGA of the component. The cable may be configured to be coupled to the BGA of the component.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 18, 2021
    Inventors: Antonio De La Rosa, Todd Albertson
  • Publication number: 20200260575
    Abstract: A foldable modular flex circuit for attaching to at least one component. The flex circuit may comprise a central area and at least one tab depending from the central area. The central area may comprise a cable attachment section configured to electrically couple to at least one coaxial cable. A first tab may depend from the central area and is configured to electrically couple to a ball grid array (BGA) of the component. A second pair of tabs may depend from the central area and are configured to electrically couple to an additional at least one component, wherein each tab depends substantially perpendicular from the central area.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Inventors: Antonio De La Rosa, Todd Albertson
  • Patent number: 10578647
    Abstract: Embodiments may include systems and methods for manufacturing a probe for wafer sorting or die testing. A probe for wafer sorting or die testing may include a probe body and a probe tip. The probe body may include a probe core and a probe plating layer around the probe core. The probe core may include a first material, and the probe plating layer may include a second material. The probe tip may be next to the probe core of the probe body and may include the first material. In addition, the probe tip may have an end surface that is smaller than a surface of the probe core, and larger than a single point. A probe-manufacturing device may include a forging unit, a clipping unit, and an actuation mechanism to control the forging unit and the clipping unit. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Todd Albertson, Jin Yang, Donald E. Edenfeld
  • Publication number: 20190101569
    Abstract: Embodiments may include systems and methods for manufacturing a probe for wafer sorting or die testing. A probe for wafer sorting or die testing may include a probe body and a probe tip. The probe body may include a probe core and a probe plating layer around the probe core. The probe core may include a first material, and the probe plating layer may include a second material. The probe tip may be next to the probe core of the probe body and may include the first material. In addition, the probe tip may have an end surface that is smaller than a surface of the probe core, and larger than a single point. A probe-manufacturing device may include a forging unit, a clipping unit, and an actuation mechanism to control the forging unit and the clipping unit. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Todd Albertson, Jin Yang, Donald E. Edenfeld
  • Patent number: 10096953
    Abstract: Methods and apparatus for a shielded and grounded cable assembly include a coaxial cable assembly having a uniform spacing between cables to pre-align the cable assembly in an array corresponding to a connection layout of at a source end. The cable assembly includes a plurality of coaxial cables with exposed shields that are commonly grounded to a drain wire. The cable assembly may also be configured to be connected vertically/perpendicularly to a ball grid array or edge connected to a circuit board.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 9, 2018
    Assignee: High Speed Interconnects, LLC
    Inventors: Donovan Finnestad, James Alexander Moss, Antonio De La Rosa, Todd Albertson
  • Patent number: 8962482
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Todd Albertson, Darin Miller, Mark Anderson
  • Patent number: 7642651
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: January 5, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Todd Albertson, Darin Miller, Mark Anderson
  • Patent number: 7375033
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Todd Albertson, Darin Miller, Mark Anderson
  • Publication number: 20070144411
    Abstract: A feeder assembly (28) for projecting solid fuel, such as coal (24), into a combustion chamber (11) of a furnace (10) includes a distributor (44) and a feeder (42) disposed in a housing (40). The distributor (44) includes a rotor (48) having blades (46) extending outwardly therefrom, and the rotor (48) is rotatable to project the solid fuel into the combustion chamber (11). The feeder (42) includes a conveyor assembly (50) for providing the solid fuel to the rotor (48). The housing (40) includes an aperture (41) disposed therein, through which the solid fuel is projected into the combustion chamber (11). The housing (40) also includes a portion (45) movable between: a first position wherein the aperture (41) is open to allow the solid fuel to be projected into the combustion chamber (11), and a second position wherein the movable portion (45) closes the aperture (41) to shield the rotor (48) from heat emitted from the combustion chamber (11) and allow maintenance and/or replacement of the distributor (44).
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventors: Richard Matysik, James Nelligan, Todd Albertson, Michael Grochowski
  • Publication number: 20070069262
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Application
    Filed: November 16, 2006
    Publication date: March 29, 2007
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Todd Albertson, Darin Miller, Mark Anderson
  • Publication number: 20070020928
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Application
    Filed: September 8, 2006
    Publication date: January 25, 2007
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Todd Albertson, Darin Miller, Mark Anderson
  • Publication number: 20060002161
    Abstract: The present application relates to apparatus and methods for burn-in and other diagnostics performed on integrated circuits. In one embodiment, the invention includes a plurality of sockets, each to hold an integrated circuit (IC), and coupling power to the respective IC from a remote power supply, a plurality of voltage detectors, each coupled to a socket to sense the voltage of the power coupled to the respective IC, and a plurality of remote voltage regulators, each coupled between the power supply and a respective socket, to receive the sensed voltage from the respective voltage detector and to adjust the voltage of the respective coupled power in accordance therewith.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Daniel Dangelo, Todd Albertson, Hon Kon, Jin Pan
  • Publication number: 20050106885
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Todd Albertson, Darin Miller, Mark Anderson