Patents by Inventor Todd C. Mendenhall

Todd C. Mendenhall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6570626
    Abstract: A video system is disclosed that processes OSD images and displays the OSD images on a display. At least some of the OSD images are represented by data sets that do not include a color palette. Each OSD data set includes a header comprising multiple bits of status and control information. One of the control bits indicates whether the OSD data set includes a color palette. Preferably that control bit is set to indicate no color palette in present and cleared to indicate the inclusion of a color palette in the OSD data set. By not including a color palette in an OSD data set, the corresponding OSD image can be represented with a smaller data set and can be transferred across a bus with a smaller bandwidth. If the control bit is set, indicating the absence of a color palette in the OSD data set, a color palette included in another OSD data set is used instead to draw the desired OSD image.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: May 27, 2003
    Assignee: LSI Logic Corporation
    Inventors: Todd C. Mendenhall, Katsuhiro Muromachi
  • Patent number: 6483951
    Abstract: A video filter unit is described which is implemented as a three-stage filter comprising a vertical filter, a horizontal decimation filter, and a horizontal interpolation filter. The three stages of the filter unit preferably connect serially with the vertical filter comprising the input first stage, the horizontal decimation filter comprising the second stage and the horizontal interpolation filter comprising the third stage which provides the output filtered image from the filter unit. As such, the video data to be filtered is provided to the vertical filter which provides its output to the horizontal decimation filter. After horizontal decimation, which can be disabled if desired (i.e., no horizontal decimation), the video data is then horizontally interpolated. The horizontal interpolation filter stage can also be disabled if desired. The vertical filter can be configured to operate either as a decimation filter or an interpolation filter.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: November 19, 2002
    Assignee: LSI Logic Corporation
    Inventors: Todd C Mendenhall, Darren D. Neuman
  • Patent number: 6424381
    Abstract: A video decoder decimates an input image to produce a decimated output image. The video decoder uses approximately every line of pixels in the input image to compute the lines of pixels in the decimated image. The video decoder includes a vertical decimation filter that computes an average, and preferably a weighted average, of luminance (luma) values associated with pixels from each of four lines in the input image. The decimation filter preferably computes a weighted average of lumas from four adjacent lines of pixels from the input image which may represent a frame or a field of video data. The weighted average preferably uses coefficients that weight each luma in the calculation differently. After calculating all of the luma values for a particular line of the decimated image, the line number associated with the first of the four adjacent lines is incremented by four (in a field-based system) to determine the initial line number for calculating the next line in the decimated image.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: July 23, 2002
    Assignee: LSI Logic Corporation
    Inventors: Todd C. Mendenhall, Darren D. Neuman
  • Patent number: 6341198
    Abstract: A memory buffer allowing preliminary access to an upstream data portion in a data stream and a method for allowing the access. This memory buffer is a “peek-ahead” FIFO comprising a data input that receives a data stream, a data output, a circular FIFO buffer that stores data from the input at a circulating read location and provided data from a circulating write location to the data output. The memory buffer also has read and write pointers that indicate the read and write locations in the FIFO buffer. If the upstream data portion is stored in the memory buffer, the read pointer can temporarily advance by an offset number of memory locations to allow reading of the upstream data portion. In one embodiment, this memory buffer is included in a DVD decoder and is used to identify the type of an incoming packet before the entire header of the packet is processed. Also described is a method and system for parsing data words from an interleaved byte stream.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Todd C. Mendenhall, Manabu Gouzu
  • Patent number: 6278838
    Abstract: A memory buffer allowing preliminary access to an upstream data portion in a data stream and a method for allowing the access. This memory buffer is a “peek-ahead” FIFO comprising a data input that receives a data stream, a data output, a circular FIFO buffer that stores data from the input at a circulating read location and provided data from a circulating write location to the data output. The memory buffer also has read and write pointers that indicate the read and write locations in the FIFO buffer. If the upstream data portion is stored in the memory buffer, the read pointer can temporarily advance by an offset number of memory locations to allow reading of the upstream data portion. In one embodiment, this memory buffer is included in a DVD decoder and is used to identify the type of an incoming packet before the entire header of the packet is processed. Also described is a method and system for parsing data words from an interleaved byte stream.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: August 21, 2001
    Assignee: LSI Logic Corporation
    Inventors: Todd C. Mendenhall, Manabu Gouzu
  • Patent number: 6272497
    Abstract: A video filter processes pixel data by storing multiple lines of pixel data in a memory buffer and computes a weighted average of the data using a plurality of multipliers and accumulators. The pixel data which, for example, may represent luminance and/or chrominance values is stored in the buffer in an interleaved fashion. Preferably multiple lines of pixel data is stored in a single buffer, thereby reducing the number of traces that would otherwise be required if a separate buffer was used for each line of pixel data.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: August 7, 2001
    Assignee: LSI Logic Corporation
    Inventors: Todd C. Mendenhall, Gregg Dierke
  • Patent number: 6133960
    Abstract: A video processing system that processes vertical column of pixels from individual fields is disclosed. The video processing system processes pixels from an even field independent of the pixels in the odd field, and vice versa. The video processing system preferably includes a system memory for storing fields of input video images and a vertical filter coupled to the system memory via a data bus. The field data is retrieved from the system memory by the vertical filter and processed as individual fields. The vertical filter preferably calculates a 2.times. enlargement of the input image, although the filter can be adapted to enlarge by different factors if desired. The enlargement process generally involves representing an input image with twice as many lines of pixels values as the initial image. The values that are used to represent the enlarged pixels are preferably weighted averages of the pixels from an input pixel field.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: October 17, 2000
    Assignee: LSI Logic Corporation
    Inventor: Todd C. Mendenhall
  • Patent number: 5903282
    Abstract: A video decoder which uses a dynamic memory allocation scheme having additional buffer read pointers for implementing a freeze mode. The additional buffer read pointers advantageously allow for implementation of a freeze mode on a dynamic memory allocation architecture. In one embodiment, the video decoder includes an MPEG bitstream decoder, FIFO buffer logic, a free segment register, and a display processor. The video decoder decodes an encoded bitstream to obtain image data for storage in an external memory, and the display processor retrieves the image data for display on a monitor. To conserve memory, the bitstream decoder stores only anchor frames as complete images in the external memory, and bi-directional images are stored in dynamically allocated memory segments. Free memory segments are determined by examination of a free segment register, and pointers to the memory segments having image data are passed to the display processor via the FIFO buffers.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: May 11, 1999
    Assignee: LSI Logic Corporation
    Inventors: Brian Schoner, Todd C. Mendenhall