Patents by Inventor Todd Dauenbaugh
Todd Dauenbaugh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742008Abstract: A memory device includes a first data driver configured to send according to a first clock signal a first data to a first data port; a second data driver configured to send according to a second clock signal a second data to a second data port, wherein the second clock signal does not match the first clock signal.Type: GrantFiled: April 26, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, Todd A. Dauenbaugh
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Publication number: 20210249058Abstract: A memory device includes a first data driver configured to send according to a first clock signal a first data to a first data port; a second data driver configured to send according to a second clock signal a second data to a second data port, wherein the second clock signal does not match the first clock signal.Type: ApplicationFiled: April 26, 2021Publication date: August 12, 2021Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, Todd A. Dauenbaugh
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Patent number: 11024349Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.Type: GrantFiled: May 1, 2019Date of Patent: June 1, 2021Assignee: Micron Technology, Inc.Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, Todd A. Dauenbaugh
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Publication number: 20190348092Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.Type: ApplicationFiled: May 1, 2019Publication date: November 14, 2019Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, Todd A. Dauenbaugh
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Patent number: 10395702Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.Type: GrantFiled: May 11, 2018Date of Patent: August 27, 2019Assignee: Micron Technology, Inc.Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, Todd A. Dauenbaugh
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Patent number: 8397129Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: GrantFiled: May 9, 2012Date of Patent: March 12, 2013Assignee: Micron Technology, Inc.Inventors: John F. Schreck, Todd A. Dauenbaugh
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Publication number: 20120221916Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: Micron Technology, Inc.Inventors: John F. Schreck, Todd A. Dauenbaugh
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Patent number: 8181086Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: GrantFiled: April 13, 2011Date of Patent: May 15, 2012Assignee: Micron Technology, Inc.Inventors: John F. Schreck, Todd A. Dauenbaugh
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Publication number: 20110191655Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Applicant: Micron Technology, Inc.Inventors: John F. Schreck, Todd A. Dauenbaugh
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Patent number: 7945840Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: GrantFiled: February 12, 2007Date of Patent: May 17, 2011Assignee: Micron Technology, Inc.Inventors: John F. Schreck, Todd A. Dauenbaugh
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Patent number: 7506226Abstract: A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is “0,” the test data bits are all “0,” and if the received bit is “1,” the test data bits are all “1.” The test data bits are applied to the ECC encoder that is used in normal operation. The ECC encoder is designed so that it generates ECC bits that have the same logic level as the test data bits. The test data bits and ECC bits are then written to a memory array and subsequently read. During the test mode, a logic circuit determines if the read data and check bits are all either “0” or “1” and outputs a corresponding test result bit from the memory device.Type: GrantFiled: May 23, 2006Date of Patent: March 17, 2009Assignee: Micron Technology, Inc.Inventors: Partha Gajapathy, Todd Dauenbaugh
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Publication number: 20080195894Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: ApplicationFiled: February 12, 2007Publication date: August 14, 2008Inventors: John F. Schreck, Todd A. Dauenbaugh
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Publication number: 20070277066Abstract: A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is “0,” the test data bits are all “0,” and if the received bit is “1,” the test data bits are all “1.” The test data bits are applied to the ECC encoder that is used in normal operation. The ECC encoder is designed so that it generates ECC bits that have the same logic level as the test data bits. The test data bits and ECC bits are then written to a memory array and subsequently read. During the test mode, a logic circuit determines if the read data and check bits are all either “0” or “1” and outputs a corresponding test result bit from the memory device.Type: ApplicationFiled: May 23, 2006Publication date: November 29, 2007Inventors: Partha Gajapathy, Todd Dauenbaugh
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Publication number: 20030028834Abstract: A method and corresponding architecture are disclosed for sharing redundant rows between banks of a memory array. The architecture is such that sub-arrays associated with different banks are alternated and coupled via a sense amp. In addition, sub-arrays belonging to the same bank are coupled via a single row decoder. This architecture allows for adjacent sub-arrays belonging to different banks to share redundant rows, thereby effectively doubling the number of redundant rows available for use in a given bank.Type: ApplicationFiled: August 1, 2001Publication date: February 6, 2003Inventors: David R. Brown, Todd A. Dauenbaugh, Partha Gajapathy
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Patent number: 6191995Abstract: A memory device includes a memory array and at least two sets of row decoders to drive row lines in the memory array. Select lines (such as row select lines) carry signals to select one or more decoders in one of the two sets of decoders. At least some of the select lines are shared between the two sets of row decoders to decrease the space needed to route signal lines in the memory array.Type: GrantFiled: August 30, 1999Date of Patent: February 20, 2001Assignee: Micron Technology, Inc.Inventors: Brian W. Huber, Todd A. Dauenbaugh