Abstract: A timing controller of a display set is integrated with an encoder for transport of analog signals between a display controller and source drivers of the display panel. The timing controller and integrated encoder are within an integrated circuit and are part of a chipset. The integrated circuit is located immediately after the SoC of a display set or is integrated within the SoC. A video signal sent to the timing controller chip is unpacked into sample values which are permuted into vectors of samples, one vector per encoder. Each vector is converted to analog, encoded and the analog levels are sent to the source drivers which decode into analog samples. Or, each digital vector is encoded and then converted to analog. A line buffer uses a memory to present a row of pixel information to the encoders. A mobile telephone has an integrated TCON with SSVT transmitter.

Abstract: A timing controller of a display set is integrated with an encoder for transport of analog signals between a display controller and source drivers of the display panel. The timing controller and integrated encoder are within an integrated circuit and are part of a chipset. The integrated circuit is located immediately after the SoC of a display set or is integrated within the SoC. A video signal sent to the timing controller chip is unpacked into sample values which are permuted into vectors of samples, one vector per encoder. Each vector is converted to analog, encoded and the analog levels are sent to the source drivers which decode into analog samples. Or, each digital vector is encoded and then converted to analog. A line buffer uses a memory to present a row of pixel information to the encoders. A mobile telephone has an integrated TCON with SSVT transmitter.

Abstract: A video stream is encoded using spread spectrum video transport and sent as an analog signal to a display of a VR visor where a decoder integrated with a source driver decodes the analog signal and drives the display. The analog signal is sent wirelessly to the display where it is received, converted to wired format, decoded and displayed. A wireless SSVT analog signal is received at the headset processor and forwarded to the VR visor for reception, conversion, decoding and display. A wireless SSVT analog signal is received at the processor, converted to wired format, sent wirelessly to the display where it is received at a receiver, converted to wired format, decoded and displayed. A video stream is stored in persistent storage on the headset processor using SSVT encoding. The decoder integrated with a source driver of a display is implemented directly on the glass of the display panel.

Abstract: A semiconductor tester high-speed system with Single Instruction-stream Multiple Data-stream (SIMD) organization, incorporating an event generator array, a plurality of pin channels for connecting to a device under test (DUT), a reconfigurable allocation switch for assignment of event generators to individual DUT pin channel connections, multi-clocking, and SIMD instruction cache. The result is a tester digital system exhibiting a maximum ratio of performance to hardware cost.

Abstract: A semiconductor tester high-speed system with Single Instruction-stream Multiple Data-stream (SIMD) organization, incorporating an event generator array, a plurality of pin channels for connecting to a device under test (DUT), a reconfigurable allocation switch for assignment of event generators to individual DUT pin channel connections, multi-clocking, and SIMD instruction cache. The result is a tester digital system exhibiting a maximum ratio of performance to hardware cost.

Abstract: This invention relates to Single Instruction-stream Multiple Data-stream (SIMD) computer architecture. A SIMD computer typically comprises one or more single-chip Processing Element (PE) modules, each having one or more PEs and interfaces to multi-chip subsystems (MCSs). The PEs bear the brunt of a SIMD computation's workload, while MCSs provide coordination among PEs.In one aspect, this invention comprises augmenting the PE module with a multiplicity of clocks so as to regulate each PE and each MCS at its maximum rate of operation. In a further aspect, this invention comprises augmenting the PE modules with the ability to store instruction sequences and to provide repeated instruction sequences at the highest possible rate within the PE module.A SIMD computer allocates a greatest possible proportion of total chip-area to PEs. As determined by the electrical characteristics of the VLSI-based implementation process, the maximum operation rates of the PEs and MCSs exceed the rate of the global system clock.