Patents by Inventor Todd E. Swanson
Todd E. Swanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8250338Abstract: A mechanism for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read, the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: GrantFiled: May 29, 2008Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Adam P. Burns, Steven L. Roberts, Christopher J Spandikow, Todd E. Swanson
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Patent number: 8024489Abstract: A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: GrantFiled: April 21, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, Peichun P. Liu, Todd E. Swanson, Thuong Q. Truong
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Patent number: 7930457Abstract: Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: GrantFiled: January 29, 2009Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, John S. Liberty, Todd E. Swanson
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Patent number: 7869459Abstract: A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: GrantFiled: May 29, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, John S Liberty, Todd E. Swanson, Thuong Q. Truong
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Patent number: 7778271Abstract: A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: GrantFiled: August 19, 2005Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, John S. Liberty, Todd E. Swanson, Thuong Q. Truong
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Publication number: 20090217300Abstract: A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: ApplicationFiled: January 29, 2009Publication date: August 27, 2009Applicant: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, John S. Liberty, Todd E. Swanson
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Patent number: 7509606Abstract: A computer implemented power optimization method that generates statistics relating to the clock gating of a set of components in a VLSI design. A set of components, including those components which are not clock gated, are identified. The generation of statistics related to clock gating testing identify whether one or more components of the set of components may be clock gated.Type: GrantFiled: April 25, 2006Date of Patent: March 24, 2009Assignee: International Business Machines CorporationInventors: Rajat Chaudhry, Tilman Gloekler, Daniel L. Stasiak, Todd E. Swanson
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Patent number: 7500039Abstract: A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: GrantFiled: August 19, 2005Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, John S. Liberty, Todd E. Swanson
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Patent number: 7493468Abstract: A method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read, the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: GrantFiled: June 1, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Adam P. Burns, Steven L. Roberts, Christopher J. Spandikow, Todd E. Swanson
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Publication number: 20080288757Abstract: A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: ApplicationFiled: May 29, 2008Publication date: November 20, 2008Applicant: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, John S. Liberty, Todd E. Swanson, Thuong Q. Truong
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Publication number: 20080244200Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: ApplicationFiled: April 21, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael N. Day, Charles R. Johns, Peichun P. Liu, Todd E. Swanson, Thuong Q. Truong
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Publication number: 20080229051Abstract: A mechanism for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: ApplicationFiled: May 29, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: Adam P. Burns, Steven L. Roberts, Christopher J. Spandikow, Todd E. Swanson
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Patent number: 7386636Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: GrantFiled: August 19, 2005Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Michael N. Day, Charles R. Johns, Peichun P. Liu, Todd E. Swanson, Thuong Q. Truong
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Publication number: 20070283037Abstract: A system and method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing are provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read, the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: ApplicationFiled: June 1, 2006Publication date: December 6, 2007Inventors: Adam P. Burns, Steven L. Roberts, Christopher J. Spandikow, Todd E. Swanson