Patents by Inventor Todd E. Takken

Todd E. Takken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NEAR-CHIP COMPLIANT LAYER FOR REDUCING PERIMETER STRESS DURING ASSEMBLY PROCESS
    Publication number: 20170170092
    Abstract: A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.
    Type: Application
    Filed: January 23, 2017
    Publication date: June 15, 2017
    Inventors: Mark D. Schultz, Todd E. Takken, Shurong Tian, Yuan Yao
  • HIGH-DENSITY, FAIL-IN-PLACE SWITCHES FOR COMPUTER AND DATA NETWORKS
    Publication number: 20170155598
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • DISTRIBUTED SERIALIZED DATA BUFFER AND A MEMORY MODULE FOR A CASCADABLE AND EXTENDED MEMORY SUBSYSTEM
    Publication number: 20170115930
    Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: Paul W. COTEUS, Daniel M. DREPS, Charles A. KILMER, Kyu-hyoun KIM, Warren E. MAULE, Todd E. TAKKEN
  • High-density, fail-in-place switches for computer and data networks
    Patent number: 9634959
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
    Publication number: 20170075592
    Abstract: A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus. Bits are read from the memory device over a read channel to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • Nonvolatile memory interface for metadata shadowing
    Patent number: 9569109
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John K. Debrosse, Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge
  • Near-chip compliant layer for reducing perimeter stress during assembly process
    Patent number: 9570373
    Abstract: A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Schultz, Todd E. Takken, Shurong Tian, Yuan Yao
  • NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
    Publication number: 20170017396
    Abstract: A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 19, 2017
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • Nonvolatile memory interface for metadata shadowing
    Patent number: 9496018
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John K. Debrosse, Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge
  • EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK
    Publication number: 20160316001
    Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
    Type: Application
    Filed: May 20, 2016
    Publication date: October 27, 2016
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger, Robert M. Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E. Takken
  • BURST RESISTANT THIN WALL HEAT SINK
    Publication number: 20160290727
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The planar top member has a plurality of stamped indent formations at a plurality of locations, each indent formation providing a contact surface such that the planar top member is affixed to the bottom member by braze or solder at each contact surface. Alternatively, the planar bottom member also has a plurality of stamped indent formations in alignment with indent formations of the top member. The planar top member is affixed to the bottom member by brazing or soldering each respective contact surface of an indent formation of the planar top member to an opposing contact surface of a corresponding indent formation of the parallel planar bottom member.
    Type: Application
    Filed: August 4, 2015
    Publication date: October 6, 2016
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
    Publication number: 20160293241
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • FLEXIBLE COLD PLATE WITH ENHANCED FLEXIBILITY
    Publication number: 20160290728
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The joined planar top and bottom members have a sidewall structure of reduced height (and generally the height of the cold plate) between active areas in order to improve flexibility. The stiffness of the sidewalls is reduced by very advantageously reduce the height of the sidewalls. In one embodiment, the sidewalls are shorter in height corresponding to regions only between active areas. Alternatively, the sidewalls are of reduced height everywhere by insetting the active areas within the top and/or bottom sheets.
    Type: Application
    Filed: August 4, 2015
    Publication date: October 6, 2016
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
    Publication number: 20160291870
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 6, 2016
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • Embedding global and collective in a torus network with message class map based tree path selection
    Patent number: 9374414
    Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger, Robert M. Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E. Takken
  • COLLECTIVE NETWORK FOR COMPUTER STRUCTURES
    Publication number: 20160105262
    Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Inventors: Matthias A. Blumrich, Paul W. Coteus, Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Dirk Hoenicke, Todd E. Takken, Burkhard D. Steinmacher-Burow, Pavlos M. Vranas
  • Memory system connector
    Patent number: 9298395
    Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Douglas J. Joseph, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Todd E. Takken
  • Implementing inverted master-slave 3D semiconductor stack
    Patent number: 9281302
    Abstract: A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Shawn A. Hall, Todd E. Takken
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • HIGH-DENSITY, FAIL-IN-PLACE SWITCHES FOR COMPUTER AND DATA NETWORKS
    Publication number: 20150289406
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Application
    Filed: November 20, 2014
    Publication date: October 8, 2015
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian