Patents by Inventor Todd G. Backer

Todd G. Backer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5946169
    Abstract: A soft adjacent layer (SAL) vertically biased magnetoresistive (MR) sensor is disclosed. The SAL biased sensor includes at least three permanent magnet (PM) tabs (hereafter referred to as tabs). An MR sensor layer is disposed in relation to the tabs such that each of the tabs is spaced apart along a width of the MR sensor layer such that each of the tabs is in electrical and magnetic contact with the MR sensor layer to thereby stabilize the MR sensor layer. Preferably, a SAL is disposed in relation to the tabs such that each of the tabs is also spaced apart along a width of the SAL such that each of the tabs is in electrical and magnetic contact with the SAL. A spacer layer is formed between the MR sensor layer and the SAL.
    Type: Grant
    Filed: October 13, 1997
    Date of Patent: August 31, 1999
    Assignee: Seagate Technology, Inc.
    Inventors: William J. O'Kane, Gregory S. Mowry, Todd G. Backer, Herman C. Kluge
  • Patent number: 5665639
    Abstract: A rapid thermal anneal (RTA) process minimizes the intermixing of materials between a bump and a bonding pad so as to provide for a more reliable and durable interconnect between the bump and the bonding pad and so as to allow the probing of wafers prior to bumping. A barrier layer is formed over the bonding pads of devices formed over a semiconductor substrate. Bumps are then formed over the bonding pads and are annealed for a short time at a high temperature so as to soften the bumps for later assembly in a semiconductor package. As a result of this quick annealing process, the intermixing of materials between the bumps and the bonding pads is minimized. This is so despite any decreased step coverage of the barrier layer over probe marks on the bonding pads which resulted from testing the wafer. Accordingly, wafers may now be tested prior to bumping, thus saving the cost, time, and process steps typically incurred in bumping wafers having a zero or low yield of properly functioning semiconductor devices.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: September 9, 1997
    Assignee: Cypress Semiconductor Corp.
    Inventors: Bryan R. Seppala, Todd G. Backer, Lothar Maier