Abstract: A bicycle component includes a platform having a mounting arrangement adapted to be mounted to a bicycle. A solar cell array is arranged on the platform. A battery charging unit also is arranged on the platform and is operatively connected to the solar cell array.

Abstract: A method of register allocation in complier using a computer instruction set having tiered instructions that accesses differing numbers of registers makes a first preliminary register allocation attempt using an initially specified register set for each instruction. If this fails, the method identifies instructions having an initially specified limited register having a variable not register allocatable. The method makes a second preliminary register allocation attempt except using a less restrictive register set for the identified instructions. This method employs a next less restrictive register set and re-attempts preliminary register allocations for instructions with more than two levels of register restriction.

Abstract: This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and 32-bit instructions can coexist in the same fetch packet. In the prior architecture 32-bit instructions may not span a 32-bit boundary. The 16-bit instruction set is implemented with a special fetch packet header that signals whether the fetch packet includes some 16-bit instructions. This fetch packet header also has special bits that tell the hardware how to interpret a particular 16-bit instruction. These bits essentially allow overlays on the whole or part of the 16-bit instruction space. This makes the opcode space larger permitting more instructions than with a pure 16-bit opcode space.

Abstract: This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A predetermined one of these instructions is used as a special header. This special header has a unique encoding different from any normal instruction. When decoded this special header instructs decode hardware to decode this fetch packet in a special way. In one embodiment a bit field in the header signals the decode hardware whether to decode each instruction word normally or in an alternative way. The header may include extension opcode bits corresponding to each of the other instruction slots. In another embodiment another bit field signals whether to decode an instruction field as one normal length instruction or as two half-length instructions.