Patents by Inventor Todd M. Witter
Todd M. Witter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935151Abstract: Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.Type: GrantFiled: July 7, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: James E. Akiyama, John Howard, Murali Ramadoss, Gary K. Smith, Todd M. Witter, Satish Ramanathan, Zhengmin Li
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Publication number: 20230016167Abstract: Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.Type: ApplicationFiled: July 7, 2022Publication date: January 19, 2023Inventors: James E. AKIYAMA, John HOWARD, Murali RAMADOSS, Gary K. SMITH, Todd M. WITTER, Satish RAMANATHAN, Zhengmin LI
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Patent number: 11410264Abstract: Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.Type: GrantFiled: September 27, 2019Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: James E. Akiyama, John Howard, Murali Ramadoss, Gary K. Smith, Todd M. Witter, Satish Ramanathan, Zhengmin Li
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Publication number: 20220004351Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Aswin Padmanabhan, Sangeeta Ghangam Manepalli, Kiran K. Velicheti, Robert James Johnston, Chandra Konduru, Todd M. Witter
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Publication number: 20210191878Abstract: An apparatus to facilitate page translations is disclosed. The apparatus comprises a frame buffer to a plurality of pages of data, a plurality of display page tables to store virtual address to physical address translations to the pages of data in the frame buffer and a page table having a plurality of page table entries (PTEs), wherein each PTE maps to one of the plurality of display page tables.Type: ApplicationFiled: December 23, 2019Publication date: June 24, 2021Applicant: Intel CorporationInventors: Ankur N. Shah, Geethacharan Rajagopalan, Ronald W. Silvas, Todd M. Witter
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Publication number: 20210097640Abstract: Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: James E. AKIYAMA, John HOWARD, Murali RAMADOSS, Gary K. SMITH, Todd M. WITTER, Satish RAMANATHAN, Zhengmin LI
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Patent number: 9870301Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.Type: GrantFiled: March 31, 2014Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: Tsvika Kurts, Eilon Hazan, Sean T. Baartmans, Marcus R. Winston, Rony Ghattas, Arie Bernstein, Todd M. Witter, Marcelo Yuffe
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Patent number: 9304731Abstract: Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.Type: GrantFiled: December 21, 2011Date of Patent: April 5, 2016Assignee: INTEL CORPORATIONInventors: Nausheen Ansari, Todd M. Witter
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Publication number: 20150278058Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Inventors: TSVIKA KURTS, EILON HAZAN, SEAN T. BAARTMANS, MARCUS R. WINSTON, RONY GHATTAS, ARIE BERNSTEIN, TODD M. WITTER, MARCELO YUFFE
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Patent number: 9052902Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.Type: GrantFiled: September 24, 2010Date of Patent: June 9, 2015Assignee: Intel CorporationInventors: George R. Hayek, Todd M. Witter, Seh W. Kwa, Maximino Vasquez
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Publication number: 20150113308Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Applicant: INTEL CORPORATIONInventors: George R. Hayek, Todd M. Witter, Seh W. Kwa, Maximino Vasquez
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Patent number: 8959266Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.Type: GrantFiled: August 2, 2013Date of Patent: February 17, 2015Assignee: Intel CorporationInventors: Nadav Bonen, Todd M. Witter, Eran Shifer, Tomer Levy, Zvika Greenfield, Anant V. Nori
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Publication number: 20150039790Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Inventors: Nadav Bonen, Todd M. Witter, Eran Shifer, Tomer Levy, Zvika Greenfield, Anant V. Nori
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Publication number: 20140297902Abstract: Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2011Publication date: October 2, 2014Inventors: Nausheen Ansari, Todd M. Witter
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Patent number: 8823721Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.Type: GrantFiled: December 30, 2009Date of Patent: September 2, 2014Assignee: Intel CorporationInventors: Maximino Vasquez, Ravi Ranganathan, Seh W. Kwa, Todd M. Witter, Kyungtae Han, Paul S. Diefenbaugh
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Patent number: 8643658Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source.Type: GrantFiled: December 30, 2009Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Seh Kwa, Maximino Vasquez, Ravi Ranganathan, Todd M. Witter, Kyungtae Han, Paul S. Diefenbaugh
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Publication number: 20120079295Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: George R. Hayek, Todd M. Witter, Seh W. Kwa, Maximino Vasquez
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Patent number: 8072443Abstract: A system, apparatus, method and article to switch between video display modes are described. The apparatus may include a graphics device to switch between a progressive mode and an interlaced mode to display media information using a single pixel clock frequency for both modes. Other embodiments are described and claimed.Type: GrantFiled: June 29, 2005Date of Patent: December 6, 2011Assignee: Intel CorporationInventors: Maximino Vasquez, Todd M. Witter, Sylvia J. Downing, Trudy Hoekstra, Kristine M. Karnos, Zudan Shi
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Publication number: 20110157198Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Inventors: Maximino Vasquez, Ravi Ranganathan, Seh W. Kwa, Todd M. Witter, Kyungtae Han, Paul S. Diefenbaugh
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Publication number: 20110157202Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Inventors: Seh Kwa, Maximino Vasquez, Ravi Ranganathan, Todd M. Witter, Kyungtae Han, Paul S. Diefenbaugh