Patents by Inventor Todd Marquart
Todd Marquart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9269452Abstract: Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.Type: GrantFiled: July 15, 2014Date of Patent: February 23, 2016Assignee: Micron Technology, Inc.Inventor: Todd Marquart
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Patent number: 9183070Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.Type: GrantFiled: July 24, 2013Date of Patent: November 10, 2015Assignee: Micron Technology, Inc.Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert
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Publication number: 20150033087Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.Type: ApplicationFiled: July 24, 2013Publication date: January 29, 2015Applicant: Micron Technology, Inc.Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert
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Publication number: 20140362647Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.Type: ApplicationFiled: July 15, 2014Publication date: December 11, 2014Inventor: Todd Marquart
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Patent number: 8854892Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.Type: GrantFiled: November 27, 2012Date of Patent: October 7, 2014Assignee: Micron Technology, Inc.Inventor: Todd A. Marquart
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Patent number: 8804428Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.Type: GrantFiled: August 16, 2011Date of Patent: August 12, 2014Assignee: Micron Technology, Inc.Inventor: Todd Marquart
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Publication number: 20130346812Abstract: The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Shirish D. Bahirat, Todd A. Marquart
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Publication number: 20130044546Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Applicant: MICRON TECHNOLOGY, INC.Inventor: Todd Marquart
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Patent number: 8320185Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.Type: GrantFiled: March 31, 2010Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventor: Todd Marquart
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Patent number: 8199585Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.Type: GrantFiled: April 4, 2011Date of Patent: June 12, 2012Assignee: Micron Technology, Inc.Inventor: Todd Marquart
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Publication number: 20110242901Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Todd Marquart
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Patent number: 8023329Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.Type: GrantFiled: April 20, 2010Date of Patent: September 20, 2011Assignee: Micron Technology, Inc.Inventors: Seiichi Aritome, Todd Marquart
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Publication number: 20110182122Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.Type: ApplicationFiled: April 4, 2011Publication date: July 28, 2011Applicant: Micron Technology, Inc.Inventor: Todd Marquart
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Patent number: 7952936Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.Type: GrantFiled: October 27, 2009Date of Patent: May 31, 2011Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
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Patent number: 7920427Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.Type: GrantFiled: February 13, 2009Date of Patent: April 5, 2011Assignee: Micron Technology, Inc.Inventor: Todd Marquart
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Publication number: 20100208523Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Micron Technology, Inc.Inventor: Todd Marquart
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Publication number: 20100202210Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.Type: ApplicationFiled: April 20, 2010Publication date: August 12, 2010Inventors: Seiichi Aritome, Todd Marquart
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Patent number: 7715234Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.Type: GrantFiled: July 10, 2008Date of Patent: May 11, 2010Assignee: Micron Technology, Inc.Inventors: Seiichi Aritome, Todd Marquart
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Publication number: 20100046303Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.Type: ApplicationFiled: October 27, 2009Publication date: February 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
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Patent number: 7619931Abstract: Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.Type: GrantFiled: June 26, 2007Date of Patent: November 17, 2009Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich