Abstract: A method and apparatus for increasing the integrated circuit density of a thin small outline package (“TSOP”) semicondctor assembly is provided by stacking two semiconductor dice and electrically connecting the substantially centrally located bond pads of substantially identically arranged bond pads of each die to the same surface of a single lead frame. Each semiconductor die may be electrically connected to a plated, common connection surface of the lead frame. The lead frame may include downsets to properly position the semiconductor assembly within the package. Further, if bond wires are used as electrical connection elements, stitch bonding may be employed to enhance rigidity of the bond wires and to modify electrical characteristics of the electrical connection elements.

Abstract: Various embodiments for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover.

Abstract: A method of encapsulating an article having first and second surfaces, includes positioning a first molding section in a sealing relationship with the first surface of the article and positioning a second molding section adjacent the second surface of the article. The first molding section is filled first thereby forcing the second surface of the article into a sealing engagement with the second molding section. The second molding section is then filled.

Abstract: Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to form a recess. An array of electrical connection pads is located within the recess. A semiconductor die can be flip chip attached to the interposer by at least partial insertion of the semiconductor die within the recess with discrete conductive elements between bond pads of the semiconductor die and electrical connection pads of the interposer. The electrical connection pads communicate with a number of other electrical contact pads accessible elsewhere on the interposer, preferably on a lower surface thereof. A low viscosity underfill encapsulant is disposed between the semiconductor die and the interposer and around the discrete conductive elements by permitting the same to flow into the space between the die and the perimeter wall.

Abstract: A method and apparatus for encapsulating a BGA package. Specifically, a BGA package is encapsulated after the balls are attached to the package. The backside of the package having the balls disposed thereon may be completely covered by the encapsulant. The encapsulant is disposed in direct contact about a portion of the balls. A liner is provided to facilitate the formation of an unencapsulated portion of each ball. The unencapsulated portion may be used to couple the package to a system.

Abstract: A mold apparatus for encapsulating IC chips mounted on a substrate. In an exemplary embodiment a mold is provided with an upper mold platen having a plurality of cavities for encapsulating wire bonds and related interconnections on a first side of a multi-chip carrier substrate. The mold further includes a lower mold platen with a single cavity for encapsulating substantially the entire second chip side of the carrier substrate. Support elements are provided for supporting the multi-chip carrier substrate. The support elements are configured to prevent or minimize substrate deflection during the fill of the mold cavities with encapsulant material. The support elements may be integral to a mold cavity or may be removable. The support elements may further be aligned along lines representing a series of individual device packages. The molded assembly may then be cut along marks left in the encapsulant to define individual device packages.

Abstract: The invention provides improved packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. Methods of assembly are also provided. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment.

Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies secured to a single semiconductor support structure is inserted into an encapsulation mold. The mold contains a first section and a second section, which form a cavity around the assembly. The mold contains an aperture for transferring encapsulating material into the mold cavity. One of the mold sections has a design feature, such as a raised rib or groove interconnecting at approximately the separation or saw-cut regions of the individual dies of the assembly. Encapsulation material is inserted into the mold cavity until the cavity is filled. The mold section design feature shapes the top surface of the encapsulation layer. The mold is removed leaving the exterior surface of the encapsulation layer patterned with the design feature.

Abstract: A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first surface contacts the carrier. A portion of the carrier carrying the article is then positioned within a mold and a seal is formed between the mold and the carrier. The mold is then filled with an encapsulating material to form a seal between the article and the carrier.

Abstract: A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer backside laminate formed on a backside of a semiconductor die. The coating element may be formed from a somewhat compressible and, optionally, resilient material, which seals against a surface of a mold cavity while the semiconductor die assembly is being encapsulated. In this manner, the coating element prevents encapsulant material from covering at least a portion of the backside of the semiconductor die to prevent encapsulant flashing over the backside and thus improve heat dissipation characteristics of the packaged semiconductor die during operation.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer back side laminate formed on a back side of a semiconductor die is disclosed. The coating element may be formed from a somewhat compressible and, optionally, resilient material, which seals against a surface of a mold cavity while the semiconductor die assembly is being encapsulated. In this manner, the coating element prevents encapsulant material from covering at least a portion of the back side of the semiconductor die to prevent encapsulant flashing over the back side and thus improve heat dissipation characteristics of the packaged semiconductor die during operation.

Abstract: A technique for packaging multiple devices to form a multi-chip module. Specifically, a multi-chip package is coupled to an interposer to form the multi-chip module. The multi-chip package includes a plurality of integrated circuit chips coupled to a carrier. The chips are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The interposer is configured such that vias are aligned with the conductive elements. Conductive material may be disposed into the vias to provide signal paths from the integrated circuit chips to conductive balls disposed on the backside of the interposer.

Abstract: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package.

Abstract: A method and apparatus for applying a protective ring about the perimeter of an exposed die face. Specifically, a semiconductor chip is coupled to the upper surface of a substrate. The edges of the semiconductor chip are protected by a molding compound which is disposed about the perimeter of the chip and on all or a portion of the substrate. The molding system which is used to apply the protective ring comprises three molding plates and does not require a vacuum-based system to hold the package stationary during the encapsulation process. By not applying a molding compound on the top surface of the semiconductor chip, no height is added to the package.

Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.