Patents by Inventor Todd R. Younkin
Todd R. Younkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971394Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.Type: GrantFiled: February 25, 2019Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
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Patent number: 10950501Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.Type: GrantFiled: December 21, 2015Date of Patent: March 16, 2021Assignee: Intel CorporationInventors: Todd R. Younkin, Eungnak Han, Shane M. Harlson, James M. Blackwell
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Patent number: 10678137Abstract: Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.Type: GrantFiled: September 22, 2014Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Manish Chandhok, Todd R. Younkin, Sang H. Lee, Charles H. Wallace
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Publication number: 20190189500Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.Type: ApplicationFiled: February 25, 2019Publication date: June 20, 2019Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Jasmeet S. CHAWLA, Marie KRYSAK, Hui Jae YOO, Tristan A. TRONIC
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Patent number: 10269622Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.Type: GrantFiled: December 24, 2014Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Rami Hourani, Michael J. Leeson, Todd R. Younkin, Eungnak Han, Robert L. Bristol
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Patent number: 10256141Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.Type: GrantFiled: September 23, 2015Date of Patent: April 9, 2019Assignee: Intel CorporationInventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
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Publication number: 20180323078Abstract: A method including forming a target pattern of a target material on a surface of a substrate; depositing a block copolymer on the surface of the substrate, wherein one of two blocks of the block copolymer preferentially aligns to the target material and the two blocks self assemble after deposition into repeating lamellar bodies on the surface of the substrate; selectively retaining one of the two blocks of the block copolymer over the other as a polymer pattern; and patterning the substrate with the polymer pattern. An apparatus including an integrated circuit substrate including a plurality of contact points and a dielectric layer on the contact points; a target pattern formed in a surface of the dielectric layer; and a self-assembled layer of repeating alternating bodies of a block copolymer, wherein one of two blocks of the block copolymer is preferentially aligned to the target pattern.Type: ApplicationFiled: December 24, 2015Publication date: November 8, 2018Inventors: Stephanie A. BOJARSKI, Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Kranthi Kumar ELINENI, Ashish N. GAIKWAD, Paul A. NYHUS, Charles H. WALLACE, Hui Jae YOO
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Publication number: 20180323104Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.Type: ApplicationFiled: December 21, 2015Publication date: November 8, 2018Applicant: Intel CorporationInventors: Todd R. YOUNKIN, Eungnak HAN, Shane M. HARLSON, James M. BLACKWELL
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Patent number: 10109583Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.Type: GrantFiled: December 24, 2014Date of Patent: October 23, 2018Assignee: Intel CorporationInventors: Robert L. Bristol, Manish Chandhok, Jasmeet S. Chawla, Florian Gstrein, Eungnak Han, Rami Hourani, Kevin Lin, Richard E. Schenker, Todd R. Younkin
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Publication number: 20180204760Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.Type: ApplicationFiled: September 23, 2015Publication date: July 19, 2018Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Jasmeet S. (JZ) CHAWLA, Marie KRYSAK, Hui Jae YOO, Tristan A. TRONIC
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Publication number: 20170345643Abstract: Photodefinable alignment layers for chemical assisted patterning and approaches for forming photodefinable alignment layers for chemical assisted patterning are described. An embodiment of the invention may include disposing a chemically amplified resist (CAR) material over a hardmask that includes a switch component. The CAR material may then be exposed to form exposed resist portions. The exposure may produces acid in the exposed portions of the CAR material that interact with the switch component to form modified regions of the hardmask material below the exposed resist portions.Type: ApplicationFiled: December 24, 2014Publication date: November 30, 2017Inventors: Todd R. YOUNKIN, Michael J. LEESON, James M. BLACKWELL, Ernisse S. PUTNA, Marie KRYSAK, Rami HOURANI, Eungnak HAN, Robert L. BRISTOL
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Publication number: 20170263496Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.Type: ApplicationFiled: December 24, 2014Publication date: September 14, 2017Inventors: RAMI HOURANI, MICHAEL J. LEESON, TODD R. YOUNKIN, EUNGNAK HAN, ROBERT L. BRISTOL
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Publication number: 20170263551Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.Type: ApplicationFiled: December 24, 2014Publication date: September 14, 2017Inventors: ROBERT L. BRISTOL, MANISH CHANDHOK, JASMEET S. CHAWLA, FLORIAN GSTREIN, EUNGNAK HAN, RAMI HOURANI, KEVIN LIN, RICHARD E. SCHENKER, TODD R. YOUNKIN
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Publication number: 20170235228Abstract: Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.Type: ApplicationFiled: September 22, 2014Publication date: August 17, 2017Applicant: Intel CorporationInventors: Manish CHANDHOK, Todd R. YOUNKIN, Sang H. LEE, Charles H. WALLACE
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Patent number: 8551555Abstract: Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide methods for coating an object with a biocompatible coating wherein the device is suspended using a flowing gas during the coating process. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.Type: GrantFiled: December 26, 2007Date of Patent: October 8, 2013Assignee: Intel CorporationInventors: John Burghard, Carmen Campbell, Todd R. Younkin, Markus Kuhn, David Shykind, Jose Maiz
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Publication number: 20090169714Abstract: Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide methods for coating an object with a biocompatible coating wherein the device is suspended using a flowing gas during the coating process. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.Type: ApplicationFiled: December 26, 2007Publication date: July 2, 2009Inventors: John Burghard, Carmen Campbell, Todd R. Younkin, Markus Kuhn, David Shykind, Jose Maiz