Abstract: An active matrix substrate (100A) includes a TFT (20), a scanning line (11) substantially parallel to a first direction, a signal line (12) substantially parallel to a second direction which is orthogonal to the first direction, a first interlayer insulating layer (16) covering the TFT, a lower layer electrode (17) provided on the first interlayer insulating layer, a dielectric layer (18) provided on the lower layer electrode, and an upper layer electrode (19) overlapping at least a portion of the lower layer electrode via the dielectric layer. A first contact hole (31) includes a first aperture (16a) formed in the first interlayer insulating layer and a second aperture (18a) formed in the dielectric layer. A width of the first aperture along one of the first direction and the second direction is smaller than a width of the second aperture along the one direction.

Abstract: An active matrix substrate (100A) includes a TFT (20), a scanning line (11) substantially parallel to a first direction, a signal line (12) substantially parallel to a second direction which is orthogonal to the first direction, a first interlayer insulating layer (16) covering the TFT, a lower layer electrode (17) provided on the first interlayer insulating layer, a dielectric layer (18) provided on the lower layer electrode, and an upper layer electrode (19) overlapping at least a portion of the lower layer electrode via the dielectric layer. A first contact hole (31) includes a first aperture (16a) formed in the first interlayer insulating layer and a second aperture (18a) formed in the dielectric layer. A width of the first aperture along one of the first direction and the second direction is smaller than a width of the second aperture along the one direction.

Abstract: A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed over the insulating substrate (10a), a first copper layer (4) disposed over the first barrier metal layer (3), and a second barrier metal layer (5) formed of titanium and disposed over the first copper layer (4); a gate insulating layer (7) disposed covering the gate electrode (2); and a semiconductor layer (8) disposed over the gate insulating layer (7), and having a channel region (C) disposed overlapping the gate electrode (2).

Abstract: A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed over the insulating substrate (10a), a first copper layer (4) disposed over the first barrier metal layer (3), and a second barrier metal layer (5) formed of titanium and disposed over the first copper layer (4); a gate insulating layer (7) disposed covering the gate electrode (2); and a semiconductor layer (8) disposed over the gate insulating layer (7), and having a channel region (C) disposed overlapping the gate electrode (2).

Abstract: Disclosed is a thin film transistor substrate which is provided with: a plurality of source lines 11a provided to extend parallel to a substrate 10; a plurality of gate lines 13a provided to extend parallel to each other in the direction that intersects the source lines 11a; and a plurality of pixel electrodes 17a, which are arranged in a matrix along the direction wherein the source lines 11a extend and in the direction wherein the gate lines 13a extend. On each gate line 13a, a through hole Ha is provided at a part where each gate line intersects each source line 11a, and inside of the through hole Ha, a semiconductor layer 15a is provided with a gate insulating film 14a therebetween.