Patents by Inventor Tohru Daitoh
Tohru Daitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152013Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: ApplicationFiled: January 19, 2024Publication date: May 9, 2024Inventors: Yoshihito HARA, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20240154038Abstract: A semiconductor device includes a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a first semiconductor layer made of an oxide semiconductor material of the first conductivity type, a first gate insulating layer provided on the first semiconductor layer, a first gate electrode located opposite to a channel region of the first semiconductor layer with the first gate insulating layer interposed therebetween, and a first source electrode. The second TFT includes a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type, a second gate insulating layer provided on the second semiconductor layer, a second gate electrode located opposite to a channel region of the second semiconductor layer with the second gate insulating layer interposed therebetween, and a second source electrode.Type: ApplicationFiled: October 10, 2023Publication date: May 9, 2024Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
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Patent number: 11955097Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).Type: GrantFiled: December 5, 2022Date of Patent: April 9, 2024Assignee: Sharp Display Technology CorporationInventors: Jun Nishimura, Yoshihito Hara, Yohei Takeuchi, Kengo Hara, Tohru Daitoh
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Publication number: 20240112646Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.Type: ApplicationFiled: August 14, 2023Publication date: April 4, 2024Inventors: Jun NISHIMURA, Kengo HARA, Yohei TAKEUCHI, Yoshihito HARA, Tohru DAITOH
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Patent number: 11927860Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: GrantFiled: April 11, 2022Date of Patent: March 12, 2024Assignee: SHARP DISPLAY TECHNOLOGY CORPORATIONInventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
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Publication number: 20230418123Abstract: An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.Type: ApplicationFiled: June 20, 2023Publication date: December 28, 2023Inventors: Hitoshi TAKAHATA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA
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Patent number: 11830454Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal.Type: GrantFiled: January 25, 2023Date of Patent: November 28, 2023Assignee: SHARP DISPLAY TECHNOLOGY CORPORATIONInventors: Kengo Hara, Tohru Daitoh, Yoshihito Hara, Jun Nishimura, Yohei Takeuchi
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Publication number: 20230352493Abstract: An active matrix substrate includes a thin film transistor including an oxide semiconductor layer, an interlayer insulating layer covering the thin film transistor, a pixel electrode provided above the interlayer insulating layer and electrically connected to the thin film transistor, a common electrode provided between the pixel electrode and the interlayer insulating layer, a first dielectric layer provided between the common electrode and the pixel electrode, and an alignment film covering the pixel electrode. The first dielectric layer includes a plurality of openings each of which exposes a part of the common electrode and includes the alignment film positioned therein.Type: ApplicationFiled: April 27, 2023Publication date: November 2, 2023Inventors: Yoshihito HARA, Tohru DAITOH, Jun NISHIMURA, Kengo HARA, Yohei TAKEUCHI
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Patent number: 11804498Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.Type: GrantFiled: May 21, 2020Date of Patent: October 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tatsuya Kawasaki, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Teruyuki Ueda
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Patent number: 11791345Abstract: An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length L1 of the offset regions of the first TFT in a channel length direction is greater than a total length L2 of the offset regions of the second TFT in the channel length direction.Type: GrantFiled: December 22, 2021Date of Patent: October 17, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hitoshi Takahata, Tetsuo Kikuchi, Kengo Hara, Setsuji Nishimiya, Masahiko Suzuki, Tohru Daitoh
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Patent number: 11790867Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: December 7, 2022Date of Patent: October 17, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20230317739Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.Type: ApplicationFiled: April 4, 2023Publication date: October 5, 2023Inventors: Hajime IMAI, Tohru DAITOH, Yoshihito HARA, Tetsuo KIKUCHI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20230307465Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: ApplicationFiled: May 18, 2023Publication date: September 28, 2023Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA, Tetsuo KIKUCHI
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Publication number: 20230252951Abstract: An active matrix substrate includes a gate driver including a shift register including a plurality of unit circuits connected in multiple stages. Each of the plurality of unit circuits includes an output node, a first node, a first TFT including a first gate terminal supplied with the set signal, a first source terminal connected to the first node, and a first drain terminal supplied with a first power supply potential higher than a low-level potential of the set signal, and a second TFT including a second gate terminal connected to the first node, a second source terminal connected to the output node, and a second drain terminal supplied with the clock signal. The first TFT includes a semiconductor layer, and a first and a second gate electrodes disposed on a side of the semiconductor layer opposite to the substrate and connected to the first gate terminal.Type: ApplicationFiled: January 25, 2023Publication date: August 10, 2023Inventors: Kengo HARA, Tohru DAITOH, Yoshihito HARA, Jun NISHIMURA, Yohei TAKEUCHI
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Patent number: 11721704Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.Type: GrantFiled: February 7, 2022Date of Patent: August 8, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Tetsuo Kikuchi, Masamitsu Yamanaka, Yoshihito Hara, Tatsuya Kawasaki, Masahiko Suzuki, Setsuji Nishimiya
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Publication number: 20230221605Abstract: A semiconductor device including a substrate, and a first circuit supported by the substrate and including a plurality of TFTs including a first TFT, wherein the first TFT includes a semiconductor layer, a lower gate electrode located on a side of the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via a lower gate insulating layer, and an upper gate electrode located on a side opposite to the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via an upper gate insulating layer, one of the lower gate electrode and the upper gate electrode is a first gate electrode and the other is a second gate electrode, a first signal is supplied to the first gate electrode, and a second signal different from the first signal is supplied to the second gate electrode, the first TFT has a threshold voltage between a high-level potential and a low-level potential of the first signal and between a high-level potential and a low-level potential of the secType: ApplicationFiled: January 12, 2023Publication date: July 13, 2023Inventors: Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA, Takuya WATANABE, Tohru DAITOH
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Publication number: 20230215876Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.Type: ApplicationFiled: March 9, 2023Publication date: July 6, 2023Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH
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Publication number: 20230215395Abstract: A shift register includes stages each constituted by a unit circuit provided with thin-film transistors that separate a control node (i.e. a node that controls output from a unit circuit) into an output-side first control node and an input-side second control node. One of the thin-film transistors has a control terminal that is supplied with a set signal that is an output signal from a unit circuit constituting a preceding stage. The other of the thin-film transistors has a control terminal that is supplied with a reset signal that is an output signal from a unit circuit constituting a subsequent stage.Type: ApplicationFiled: December 5, 2022Publication date: July 6, 2023Inventors: Jun NISHIMURA, Yoshihito HARA, Yohei TAKEUCHI, Kengo HARA, Tohru DAITOH
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Publication number: 20230215877Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.Type: ApplicationFiled: March 9, 2023Publication date: July 6, 2023Inventors: Kengo HARA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
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Patent number: 11695016Abstract: An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.Type: GrantFiled: July 1, 2021Date of Patent: July 4, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Daitoh, Masahiko Suzuki, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tetsuo Kikuchi