Abstract: According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.

Abstract: This obstacle detection device is mounted on a vehicle. This obstacle detection device includes a plurality of ultrasonic sensors, and a detector. The plurality of ultrasonic sensors transmits a plurality of ultrasonic waves of different frequencies to detection areas which overlap with each other at transmission timings which overlap with each other, and each of the ultrasonic sensors receives a returning ultrasonic wave. The detector identifies which one ultrasonic wave of a plurality of ultrasonic waves is reflected as the received returning ultrasonic wave, and detects a position of an obstacle existing around the vehicle.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.

Abstract: According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.

Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

Abstract: According to one embodiment, a controller writes first write data transferred from a first buffer and code data for second write data different from the first write data, the code data being transferred from a second buffer, in parallel to a plurality of physical pages corresponding to a first logical page. The controller writes code data for the first write data to a physical page corresponding to a second logical page, the second logical page being next to the first logical page, at a time of write to the nonvolatile memory following the write of the first write data and the code data for the second write data.

Abstract: According to one embodiment, a controller writes first write data transferred from a first buffer and code data for second write data different from the first write data, the code data being transferred from a second buffer, in parallel to a plurality of physical pages corresponding to a first logical page. The controller writes code data for the first write data to a physical page corresponding to a second logical page, the second logical page being next to the first logical page, at a time of write to the nonvolatile memory following the write of the first write data and the code data for the second write data.

Abstract: According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.

Abstract: According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing.

Abstract: According to one embodiment, a data storage apparatus comprises a first controller, a second controller, a third controller, and a fourth controller. The first controller controls a flash memory, writing and reading data, in units of blocks, to and from the flash memory. The second controller detects any a write-interrupted block is interrupted by the first controller. The third controller sets the write-interrupted block detected by the second controller, as a block to be refreshed in another block. The fourth controller performs the process of refreshing.

Abstract: There is provided a process for formation of a multi-layered coating film, which includes sequentially coating a first colored coating composition, a second colored coating composition and a clear coating composition (C), and simultaneously heating and curing the obtained first colored coating film, second colored coating film and clear coating film to form a multi-layered coating film, where the first colored coating composition contains (a1) a polyester resin containing a hydroxyl group, which contains 1.0-8.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

Abstract: There is provided a process for formation of a multi-layered coating film, which includes sequentially coating a first colored coating composition, a second colored coating composition and a clear coating composition (C), and simultaneously heating and curing the obtained first colored coating film, second colored coating film and clear coating film to form a multi-layered coating film, where the first colored coating composition contains (a1) a polyester resin containing a hydroxyl group, which contains 1.0-8.

Abstract: According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.

Abstract: According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing.

Abstract: According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory.

Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

Abstract: According to one embodiment, a memory control device includes a first controller, a second controller, an access module, and a response sort module. The first controller controls processing of a data access command to a nonvolatile memory from a host. The second controller controls processing assigned to the second controller between the first controller and the second controller. The access module performs data access to the nonvolatile memory in response to a command from the first controller or the second controller. When an error occurs in the data access by the access module, the response sort module returns a response to the second controller instead of the first controller.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.