Patents by Inventor Tohru Ohsaka
Tohru Ohsaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9084364Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.Type: GrantFiled: June 12, 2013Date of Patent: July 14, 2015Assignee: CANON KABUSHIKI KAISHAInventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
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Publication number: 20130343024Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.Type: ApplicationFiled: June 12, 2013Publication date: December 26, 2013Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
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Patent number: 7851900Abstract: In a stacked semiconductor package, since electric power is supplied to a second semiconductor package through a first semiconductor package, a power supply path becomes complicated and fluctuation of its inductance becomes large, whereby power bounce occurs to reduce signal quality and also prevent high speed signal communication. Therefore, according to the present invention, a first solder ball group for joint to a printed wiring board is attached to a second layer of the first semiconductor package, and a second solder ball group for joint to the first semiconductor package and a solder group for power supply for direct joint to the printed wiring board are provided on the second layer of the second semiconductor package, whereby electric power can be directly supplied from the printed wiring board.Type: GrantFiled: March 17, 2006Date of Patent: December 14, 2010Assignee: Canon Kabushiki KaishaInventors: Tohru Ohsaka, Hiroshi Kondo
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Patent number: 7839652Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.Type: GrantFiled: October 22, 2008Date of Patent: November 23, 2010Assignee: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Patent number: 7594105Abstract: This invention effectively prevents potential fluctuation in the power supply terminal of a semiconductor device, that is, noise from flowing out to a main power supply wiring. A multilayer print circuit board includes a first power supply via hole which connects to the power supply terminal of a semiconductor integrated circuit on a first surface layer and extends from the first surface layer to a second surface layer, a ground via hole which connects to a ground conductive layer, extends from the ground conductive layer to the second surface layer, and connects to the first power supply via hole on the second surface layer through a bypass capacitor, a first clearance hole which is formed in a power supply conductive layer, and a second clearance hole which is formed in the ground conductive layer. The first clearance hole is larger than the second clearance hole.Type: GrantFiled: December 5, 2006Date of Patent: September 22, 2009Assignee: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Publication number: 20090051015Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.Type: ApplicationFiled: October 22, 2008Publication date: February 26, 2009Applicant: CANON KABUSHIKI KAISHAInventor: Tohru Ohsaka
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Patent number: 7495928Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.Type: GrantFiled: December 19, 2007Date of Patent: February 24, 2009Assignee: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Publication number: 20080128873Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.Type: ApplicationFiled: December 19, 2007Publication date: June 5, 2008Applicant: CANON KABUSHIKI KAISHAInventor: Tohru Ohsaka
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Patent number: 7349224Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.Type: GrantFiled: March 31, 2005Date of Patent: March 25, 2008Assignee: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Patent number: 7277298Abstract: According to the invention, even when high-speed differential signal pins are arranged on the inner side of a BGA, they can be wired on a printed wiring board at a low cost. In a multi-terminal device (1) having one surface where a large number of connection terminals are arrayed planarly, terminals (3) that need not be electrically connected individually are arranged between differential signal terminals (2) of the multi-terminal device and the periphery of the multi-terminal device.Type: GrantFiled: September 27, 2005Date of Patent: October 2, 2007Assignee: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Publication number: 20070136618Abstract: This invention effectively prevents potential fluctuation in the power supply terminal of a semiconductor device, that is, noise from flowing out to a main power supply wiring. A multilayer print circuit board includes a first power supply via hole which connects to the power supply terminal of a semiconductor integrated circuit on a first surface layer and extends from the first surface layer to a second surface layer, a ground via hole which connects to a ground conductive layer, extends from the ground conductive layer to the second surface layer, and connects to the first power supply via hole on the second surface layer through a bypass capacitor, a first clearance hole which is formed in a power supply conductive layer, and a second clearance hole which is formed in the ground conductive layer. The first clearance hole is larger than the second clearance hole.Type: ApplicationFiled: December 5, 2006Publication date: June 14, 2007Inventor: Tohru Ohsaka
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Patent number: 7199308Abstract: A multi-layered printed wiring board, capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises, has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, the wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.Type: GrantFiled: September 27, 2004Date of Patent: April 3, 2007Assignee: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Publication number: 20060208348Abstract: In a stacked semiconductor package, since electric power is supplied to a second semiconductor package through a first semiconductor package, a power supply path becomes complicated and fluctuation of its inductance becomes large, whereby power bounce occurs to reduce signal quality and also prevent high speed signal communication. Therefore, according to the present invention, a first solder ball group for joint to a printed wiring board is attached to a second layer of the first semiconductor package, and a second solder ball group for joint to the first semiconductor package and a solder group for power supply for direct joint to the printed wiring board are provided on the second layer of the second semiconductor package, whereby electric power can be directly supplied from the printed wiring board.Type: ApplicationFiled: March 17, 2006Publication date: September 21, 2006Inventors: Tohru Ohsaka, Hiroshi Kondo
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Publication number: 20060065965Abstract: According to the invention, even when high-speed differential signal pins are arranged on the inner side of a BGA, they can be wired on a printed wiring board at a low cost. In a multi-terminal device (1) having one surface where a large number of connection terminals are arrayed planarly, terminals (3) that need not be electrically connected individually are arranged between differential signal terminals (2) of the multi-terminal device and the periphery of the multi-terminal device.Type: ApplicationFiled: September 27, 2005Publication date: March 30, 2006Inventor: Tohru Ohsaka
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Publication number: 20050230823Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.Type: ApplicationFiled: March 31, 2005Publication date: October 20, 2005Applicant: CANON KABUSHIKI KAISHAInventor: Tohru Ohsaka
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Publication number: 20050039947Abstract: A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.Type: ApplicationFiled: September 27, 2004Publication date: February 24, 2005Applicant: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Patent number: 6800814Abstract: A multi-layered printed wiring board capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.Type: GrantFiled: January 16, 2002Date of Patent: October 5, 2004Assignee: Canon Kabushiki KaishaInventor: Tohru Ohsaka
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Publication number: 20020108779Abstract: A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.Type: ApplicationFiled: January 16, 2002Publication date: August 15, 2002Inventor: Tohru Ohsaka
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Patent number: 6335866Abstract: A printed wiring board unit for use with an electronic apparatus in which the unit is formed by a power circuit and a digital circuit. The power circuit is constructed as a power circuit board made of a single-sided board, and the digital circuit is a high density digital circuit board which is smaller than the power circuit board. The digital circuit board is formed into a module by mounting thereon an IC, etc., which operates at the highest internal clock frequency. This reduced digital circuit board is mounted onto the power circuit board with spacing between parts in a layered structure, thereby improving unwanted radiation noise characteristics without increasing costs.Type: GrantFiled: October 7, 1998Date of Patent: January 1, 2002Assignee: Canon Kabushiki KaishaInventors: Tohru Ohtaki, Tohru Ohsaka
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Patent number: 5973929Abstract: A circuit board having a printed capacitor whose capacitance is easily adjusted includes a plurality of through-holes arranged in arrays and electrically connected to each other via conductive films. Therefore, first and second electrode portions are arranged to oppose each other, and form a printed capacitor. The capacitance of the capacitor can be adjusted by the number and diameter of through-holes, and the interval between each two adjacent through-holes. Therefore, even when a large-capacitance capacitor is to be formed, the printed capacitor can be rendered compact.Type: GrantFiled: November 19, 1997Date of Patent: October 26, 1999Assignee: Canon Kabushiki KaishaInventors: Tomoyasu Arakawa, Toru Otaki, Yasushi Takeuchi, Hideho Inagawa, Yoshimi Terayama, Tohru Ohsaka