Patents by Inventor Tokihisa Kaneguchi
Tokihisa Kaneguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411429Abstract: An imaging device according to an embodiment of the present disclosure includes: a first semiconductor layer including, for each pixel, a photoelectric conversion section and a charge accumulation section that accumulates signal charge generated in the photoelectric conversion section; a second semiconductor layer stacked on the first semiconductor layer and having a first surface provided with a pixel transistor, in which the pixel transistor has a three-dimensional structure and reads the signal charge from the charge accumulation section; and a through-wiring line that directly couples the charge accumulation section and a gate electrode of the pixel transistor to each other.Type: ApplicationFiled: October 20, 2021Publication date: December 21, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Keiichi NAKAZAWA, Takashi KOJIMA, Shinichi IMAI, Tokihisa KANEGUCHI, Koichiro SAGA, Kai TOKUHIRO, Takaaki HIRANO
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Publication number: 20230335574Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Tokihisa KANEGUCHI
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Patent number: 11735615Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.Type: GrantFiled: May 14, 2019Date of Patent: August 22, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki Masuda, Tokihisa Kaneguchi
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Publication number: 20230253427Abstract: The present technology relates to a semiconductor package and a method for manufacturing the semiconductor package that are capable of improving the quality of the semiconductor package having a WCSP structure. A semiconductor package includes: a semiconductor substrate including a light receiving element; an on-chip lens disposed on an incident surface side of the semiconductor substrate; a resin layer in contact with a central portion including a most protruding portion of the on-chip lens; and a glass substrate in contact with a surface of the resin layer opposite to a surface of the resin layer in contact with the on-chip lens, wherein a space is provided between a peripheral portion around the central portion of the on-chip lens and the resin layer. The present technology can be applied to, for example, an imaging element.Type: ApplicationFiled: June 23, 2021Publication date: August 10, 2023Inventors: YOSHIAKI MASUDA, TOKIHISA KANEGUCHI
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Publication number: 20230103730Abstract: A solid-state imaging device that includes a first substrate, one or multiple second substrates, a first wiring layer, a second wiring layer, and a first alignment part. The first substrate includes a first semiconductor substrate with multiple photoelectric conversion sections, and a multilayer wiring layer. The one or multiple second substrates are attached to the first substrate with the multilayer wiring layer interposed therebetween. The first wiring layer is in the multilayer wiring layer and includes multiple first thin metal wires formed at substantially the same first pitches. The second wiring layer is stacked above the first wiring layer in the multilayer wiring layer and includes multiple second thin metal wires formed between the multiple first thin metal wires at substantially the same second pitches in a plan view. The first alignment part is formed above the second wiring layer in the multilayer wiring layer.Type: ApplicationFiled: March 17, 2021Publication date: April 6, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Tokihisa KANEGUCHI, Kan SHIMIZU
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Patent number: 11515349Abstract: A semiconductor unit includes: a semiconductor substrate; a first groove provided in the semiconductor substrate, having a first width W1 and extending in a first direction; and a second groove provided in the semiconductor substrate in communication with the first groove, having a second width W2 different from the first width, and extending in a second direction that intersects the first direction, in which one of the first groove and the second groove is used for alignment.Type: GrantFiled: January 8, 2019Date of Patent: November 29, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Tokihisa Kaneguchi
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Publication number: 20210249463Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.Type: ApplicationFiled: May 14, 2019Publication date: August 12, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Tokihisa KANEGUCHI
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Publication number: 20210057476Abstract: A semiconductor unit includes: a semiconductor substrate; a first groove provided in the semiconductor substrate, having a first width W1 and extending in a first direction; and a second groove provided in the semiconductor substrate in communication with the first groove, having a second width W2 different from the first width, and extending in a second direction that intersects the first direction, in which one of the first groove and the second groove is used for alignment.Type: ApplicationFiled: January 8, 2019Publication date: February 25, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Tokihisa KANEGUCHI
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Patent number: 10804313Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: GrantFiled: June 6, 2018Date of Patent: October 13, 2020Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
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Publication number: 20180286911Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Applicant: Sony CorporationInventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
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Patent number: 10026769Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: GrantFiled: September 19, 2014Date of Patent: July 17, 2018Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
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Publication number: 20160233264Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: ApplicationFiled: September 19, 2014Publication date: August 11, 2016Applicant: SONY CORPORATIONInventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
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Publication number: 20150049318Abstract: An optical element includes a surface on which a plurality of structures is provided. The plurality of structures is provided to be fluctuated in a random direction from a lattice point at an interval which is equal to or shorter than a wavelength of visible light.Type: ApplicationFiled: August 11, 2014Publication date: February 19, 2015Applicant: Sony CorporationInventors: Kazuya Hayashibe, Masamitsu Kageyama, Tokihisa Kaneguchi
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Patent number: 8410569Abstract: A solid-state imaging device includes a first substrate including a light-sensing portion configured to perform photoelectric conversion of incident light and a wiring portion provided on a light-incident side; an optically transparent second substrate provided on a wiring portion side of the first substrate at a certain distance; a through-hole provided in the first substrate; a through-via provided in the through-hole; a front-surface-side electrode connected to the through-via and provided on a front surface of the first substrate; a back-surface-side electrode connected to the through-via and provided on a back surface of the first substrate; and a stopper electrode provided on the front-surface-side electrode and filling a space between the front-surface-side electrode and the second substrate.Type: GrantFiled: July 23, 2010Date of Patent: April 2, 2013Assignee: Sony CorporationInventors: Ikuo Yoshihara, Masaya Nagata, Naoto Sasaki, Taku Umebayashi, Hiroshi Takahashi, Yoichi Otsuka, Isaya Kitamura, Tokihisa Kaneguchi, Keishi Inoue, Toshihiko Hayashi, Hiroyasu Matsugai, Mayoshi Aonuma, Hiroshi Yoshioka
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Publication number: 20110024858Abstract: A solid-state imaging device includes a first substrate including a light-sensing portion configured to perform photoelectric conversion of incident light and a wiring portion provided on a light-incident side; an optically transparent second substrate provided on a wiring portion side of the first substrate at a certain distance; a through-hole provided in the first substrate; a through-via provided in the through-hole; a front-surface-side electrode connected to the through-via and provided on a front surface of the first substrate; a back-surface-side electrode connected to the through-via and provided on a back surface of the first substrate; and a stopper electrode provided on the front-surface-side electrode and filling a space between the front-surface-side electrode and the second substrate.Type: ApplicationFiled: July 23, 2010Publication date: February 3, 2011Applicant: SONY CORPORATIONInventors: Ikuo Yoshihara, Masaya Nagata, Naoto Sasaki, Taku Umebayashi, Hiroshi Takahashi, Yoichi Otsuka, Isaya Kitamura, Tokihisa Kaneguchi, Keishi Inoue, Toshihiko Hayashi, Hiroyasu Matsugai, Masayoshi Aonuma, Hiroshi Yoshioka