Patents by Inventor Tolga Ozguner
Tolga Ozguner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9978118Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.Type: GrantFiled: January 25, 2017Date of Patent: May 22, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam James Muff, Miguel Comparan, Ryan Scott Haraden, Christopher Jon Johnson
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Patent number: 9747225Abstract: An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.Type: GrantFiled: May 5, 2015Date of Patent: August 29, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Robert Allen Shearer, Elene Terry, Jonathan Ross
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Publication number: 20160328339Abstract: An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.Type: ApplicationFiled: May 5, 2015Publication date: November 10, 2016Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Robert Allen Shearer, Elene Terry, Jonathan Ross
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Patent number: 8219745Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.Type: GrantFiled: December 2, 2004Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Mark David Bellows, Kent Harold Haselhorst, Ryan Abel Heakendorf, Paul Allen Ganfield, Tolga Ozguner
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Patent number: 8213428Abstract: A method is provided for address mapping in a network processor. The method includes the steps of (1) determining a port number of a port that receives a data cell; (2) determining a virtual path identifier and a virtual channel identifier for the data cell; and (3) creating a first index based on at least one of the port number, the virtual path identifier and the virtual channel identifier. The method further includes (1) accessing one of a plurality of entries stored in a first on-chip memory using the first index; (2) creating a second index based on the accessed entry of the first on-chip memory; and (3) accessing an entry of a second memory based on the second index. Numerous other aspects are provided.Type: GrantFiled: July 24, 2003Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Gerald G. Fagerness, Kerry C. Imming, Brian M. McKevett, James F. Mikos, Tolga Ozguner
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Patent number: 8170024Abstract: A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.Type: GrantFiled: November 5, 2007Date of Patent: May 1, 2012Assignee: International Business Machines CorporationInventors: Kerry Christopher Imming, John David Irish, Joseph Franklin Logan, Tolga Ozguner, Michael Steven Siegel
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Patent number: 7925823Abstract: A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.Type: GrantFiled: October 19, 2007Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: Mark David Bellows, Kent Harold Haselhorst, Paul Allen Ganfield, Tolga Ozguner
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Patent number: 7761682Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.Type: GrantFiled: August 13, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Melissa Ann Barnum, Mark David Bellows, Paul Allen Ganfield, Lonny Lambrecht, Tolga Ozguner
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Patent number: 7757006Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.Type: GrantFiled: November 21, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Kerry Christopher Imming, John David Irish, Tolga Ozguner, Andrew Henry Wottreng
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Patent number: 7757040Abstract: A command translation method, apparatus and system are provided for interfacing a processor and a memory. The processor initiates a memory system command in an extreme data rate (XDR) command format which is automatically converted by the command translation method, apparatus and system into a memory system command in a double data rate (DDR) format for forwarding to the memory. Associated with converting the memory system command to the DDR command format is controlling timing of one or more signals presented to the memory interface, the one or more signals being associated with processing the memory system command in the DDR command format. The processor has associated therewith an XDR memory interface controller which adjusts one or more timing parameters of the memory system command in the XDR command format so that DDR timing requirements for the memory system command in the DDR command format are met.Type: GrantFiled: March 1, 2007Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Mark D. Bellows, John D. Irish, David A. Norgaard, Tolga Ozguner
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Patent number: 7752379Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.Type: GrantFiled: January 6, 2009Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Ryan Abel Heckendorf, Tolga Ozguner
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Patent number: 7669028Abstract: Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.Type: GrantFiled: February 7, 2006Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Mark D. Bellows, Brian M. McKevett, Tolga Ozguner
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Publication number: 20090144452Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.Type: ApplicationFiled: November 21, 2008Publication date: June 4, 2009Applicant: International Business Machines CorporationInventors: Kerry Christopher Imming, John David Irish, Tolga Ozguner, Andrew Henry Wottreng
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Publication number: 20090119442Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.Type: ApplicationFiled: January 6, 2009Publication date: May 7, 2009Applicant: International Business Machines CorporationInventors: Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Ryan Abel Heckendorf, Tolga Ozguner
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Patent number: 7487318Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.Type: GrantFiled: September 7, 2007Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Ryan Abel Heckendorf, Tolga Ozguner
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Patent number: 7475161Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.Type: GrantFiled: September 4, 2003Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Kerry Christopher Imming, John David Irish, Tolga Ozguner, Andrew Henry Wottreng
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Patent number: 7467277Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.Type: GrantFiled: February 7, 2006Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Melissa Ann Barnum, Mark David Bellows, Paul Allen Ganfield, Lonny Lambrecht, Tolga Ozguner
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Publication number: 20080307184Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.Type: ApplicationFiled: August 13, 2008Publication date: December 11, 2008Inventors: Melissa Ann Barnum, Mark David Bellows, Paul Allen Ganfield, Lonny Lambrecht, Tolga Ozguner
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Publication number: 20080183925Abstract: A command translation method, apparatus and system are provided for interfacing a processor and a memory. The processor initiates a memory system command in an extreme data rate (XDR) command format which is automatically converted by the command translation method, apparatus and system into a memory system command in a double data rate (DDR) format for forwarding to the memory. Associated with converting the memory system command to the DDR command format is controlling timing of one or more signals presented to the memory interface, the one or more signals being associated with processing the memory system command in the DDR command format. The processor has associated therewith an XDR memory interface controller which adjusts one or more timing parameters of the memory system command in the XDR command format so that DDR timing requirements for the memory system command in the DDR command format are met.Type: ApplicationFiled: March 1, 2007Publication date: July 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark D. Bellows, John D. Irish, David A. Norgaard, Tolga Ozguner
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Publication number: 20080183916Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Inventors: Mark David Bellows, Paul Allen Ganfield, Ryan Abel Heckendorf, John David Irish, David Alan Norgaard, Ibrahim Abdel-Rahman Ouda, Tolga Ozguner