Abstract: In one embodiment, a method for sensing an image of a scene includes receiving incident light at a image sensing device including an array of at least two regions of pixel elements, providing one or more control parameters where each of the control parameters modifies the sensitivity of the pixel elements, generating control signals for the one or more control parameter for each region of pixel elements where the sensitivity of the pixel elements is varied on a region by region basis. In another embodiment, method for sensing an image of a scene includes generating control signals for controlling two or more control parameters for controlling the pixel elements of an entire array to provide continuous fine grain control of the sensitivity of the pixel elements.

Abstract: In one embodiment, a method for sensing an image of a scene includes receiving incident light at a image sensing device including an array of at least two regions of pixel elements, providing one or more control parameters where each of the control parameters modifies the sensitivity of the pixel elements, generating control signals for the one or more control parameter for each region of pixel elements where the sensitivity of the pixel elements is varied on a region by region basis. In another embodiment, method for sensing an image of a scene includes generating control signals for controlling two or more control parameters for controlling the pixel elements of an entire array to provide continuous fine grain control of the sensitivity of the pixel elements.

Abstract: A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets labeled with packet identification codes (PIDs) that are specified by a host processor. The processor separately stores the elementary stream data of each stream. A host processor interface is also provided for transferring data between an external host processor and the program clock recovery circuit. A memory manager may be provided for storing the data extracted by the processor for each elementary stream in a corresponding queue. The queues may be maintained by the memory manager in an external RAM. A descrambler interface may be provided for transferring scrambled data and data derived from conditional access information between the processor and an external descrambler.