Abstract: Embodiments of the disclosure provide a structure with a back-gate having oppositely doped semiconductor regions. The structure may include a transistor over a substrate. The transistor includes a gate structure having a gate length. A back-gate region is within the substrate below the gate structure of the transistor. The back-gate region includes a pair of doped semiconductor regions with a P-N junction therebetween. Each of the pair of semiconductor materials has a length extending substantially in parallel with respect to the gate length.

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer. The structure further includes a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer. The second FET has a source and a drain over the buried insulator layer. The structure further includes a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein.

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to floating-gate devices and methods of manufacture. The structure includes: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor over and in electrical connection to the gate electrode.

Abstract: Disclosed are a semiconductor structure, which includes a charge-trapping sidewall spacer-type non-volatile memory (CTSS-NVM) device, and a method of forming the structure. The CTSS-NVM device includes asymmetric first and second sidewall spacers on opposing sidewalls of a gate structure above a channel region in a semiconductor substrate. The second sidewall spacer is wider than the first and includes multiple dielectric spacer layers, one of which is made of a charge-trapping material, is separated from the substrate (e.g., by a thin oxide layer), and has a bottom end closest to the substrate with a maximum width that is sufficient to achieve charge-trapping for proper CTSS-NVM device operation. The CTSS-NVM device further includes an epitaxial semiconductor layer for a source/drain region on the semiconductor substrate adjacent to the first sidewall spacer and a metal silicide layer for a Schottky barrier on the semiconductor substrate adjacent to the second sidewall spacer.

Abstract: Disclosed are a semiconductor structure, which includes a charge-trapping sidewall spacer-type non-volatile memory (CTSS-NVM) device, and a method of forming the structure. The CTSS-NVM device includes asymmetric first and second sidewall spacers on opposing sidewalls of a gate structure above a channel region in a semiconductor substrate. The second sidewall spacer is wider than the first and includes multiple dielectric spacer layers, one of which is made of a charge-trapping material, is separated from the substrate (e.g., by a thin oxide layer), and has a bottom end closest to the substrate with a maximum width that is sufficient to achieve charge-trapping for proper CTSS-NVM device operation. The CTSS-NVM device further includes an epitaxial semiconductor layer for a source/drain region on the semiconductor substrate adjacent to the first sidewall spacer and a metal silicide layer for a Schottky barrier on the semiconductor substrate adjacent to the second sidewall spacer.

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to floating-gate devices and methods of manufacture. The structure includes: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor over and in electrical connection to the gate electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Abstract: One illustrative integrated circuit product disclosed herein includes at least one transistor formed on an active region of on an SOI substrate, the transistor comprising a gate that includes a gate structure, first and second source/drain regions positioned on opposite sides of the gate, the first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type, and a doped region positioned below the gate, wherein the doped region has a lateral width that is at least substantially equal to the CPP (contact-poly-pitch) dimension of the transistor and is doped with a dopant material of the first type, wherein a first portion of the doped region is positioned vertically above an interface between the active region and a buried insulation layer of the SOI substrate and a second portion of the doped region is positioned vertically below the interface.

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully depleted silicon on insulator (SOI) semiconductor structures and methods of manufacture. The structure includes: a gate structure formed over a semiconductor material; a source region adjacent to the gate structure; a drain region remote from the gate structure; and a drift region separating the gate structure from the drain region. The drift region includes an epitaxial material grown on the semiconductor material which increases the thickness of the semiconductor material in the drift region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

Abstract: Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.