Abstract: A controller for a test head module (106) of a test cell (100) includes a control signal generator, an electronic memory device, and a signal evaluation module. The control signal generator to provide control signals to a plurality of magnetic stimulator heads, which provide magnetic stimulus signals to singulated devices for testing in response to the control signals. The electronic memory device stores instructions for controlling concurrent activation of at least two of the magnetic stimulator heads for parallel testing of the singulated devices. The signal evaluation module receives electrical signals from the singulated devices. The electrical signals from the singulated devices are dependent on the magnetic stimulus signals applied to the singulated devices.

Abstract: Integrated circuits comprising an EEPROM require a large amount of time for testing, because the write time for a memory cell is very long. Notably the first test after manufacture, with the circuit still present on the wafer, is time consuming. The invention proposes a drastic reduction of the duration of the first test after manufacture by supplying a number of integrated circuits with a voltage in parallel and by providing each integrated circuit with an element whereby several block-wise write cycles for alternately "0" and "1" are executed in substantially autonomously and at the end of the first test step predetermined information is retained. This step is followed by a thermal treatment, after which the integrated circuits are individually contacted and first tested for information retention.