Patents by Inventor Tom J. Hirsch

Tom J. Hirsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6859115
    Abstract: A computer power supply system for reducing the AC impedance of a DC power supply (52) at inputs pins of a computing device (54) such as a processor. A quarter wavelength transmission line stub (58) is connected to a computing device DC power supply input pin. The stub is open circuited at its end opposite the pin. The wavelength is selected to match a frequency at which power supply impedance is known to be high. The stub appears as a low impedance at the selected frequency. Multiple stubs at different frequencies may be used to provide reduced impedance over a broader frequency band. Stubs may be formed from printed circuit board traces on a motherboard of from metalization patterns on a computing device package.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: February 22, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tom J. Hirsch, Benjamin Beker
  • Patent number: 5358604
    Abstract: The invention provides an apparatus and methods of using the apparatus to transfer conductive patterns onto substrates under conditions of heat and pressure. The apparatus comprises a master mold with a printing surface on which is produced a permanent mirror image of the conductive pattern to be created. This pattern is then coated with a loosely adherent film of conductive metal, such as copper, which is transferred onto a substrate to be printed.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: October 25, 1994
    Assignee: Microelectronics and Computer Technology Corp.
    Inventors: Charles W. C. Lin, Chung J. Lee, Tom J. Hirsch, Kimcuc T. Tran
  • Patent number: 5192581
    Abstract: A dielectric substrate is coated with a protective layer and a catalyst film is formed in a laser irradiated predetermined pattern on the protective layer so that during electroless deposition a metal is plated on the catalyst film in the predetermined pattern whether or not the dielectric has unwanted catalytic sites. The protective layer is not removed by the electroless plating bath or prior etch steps but can subsequently be stripped by a separate etch without removing the plated metal or the dielectric from the substrate.
    Type: Grant
    Filed: January 14, 1992
    Date of Patent: March 9, 1993
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Tom J. Hirsch, Charles W. C. Lin, Chung J. Lee, Heinrich G. O. Muller
  • Patent number: 5124175
    Abstract: Solder reflow on an electrical interconnect substrate between a plurality of electrical contacts. The method includes coating the contacts with tin/lead solder, depositing a wetting metal between the contacts, and heating the substrate to at least the melting point of the solder so that the solder melts, reflows across the wetting metal and connects or links the contacts. The entire surface of a customizable copper/polyimide substrate can be personalized by solder links and TAB leads from surface-mounted integrated circuits can simultaneously be soldered to the substrate.
    Type: Grant
    Filed: November 15, 1990
    Date of Patent: June 23, 1992
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Robert F. Miracky, Tom J. Hirsch, Colin A. MacKay
  • Patent number: 5084299
    Abstract: A method for patterning electroless plated metal on a polymer substrate. In a first embodiment a substrate is first coated with a polymer suitable for complexing a seed metal which can initiate electroless plating. The polymer is then mixed with a seed metal such as palladium, selectively irradiated to form the desired conductor pattern, and then etched so that the desired pattern remains. The substrate is subsequently placed in an electroless plating bath to form a metal pattern. In a second embodiment, before applying the seed metal a substrate immersed in a polymer solution suitable for complexing a seed metal can be selectively irradiated to selectively deposit polymer on the substrate, followed by applying a seed metal to form a polymer-seed metal mixture and an electroless plating bath. In addition, an alkaline chemical may be added to an acidic polymer to prevent the polymer from etching metal on the substrate.
    Type: Grant
    Filed: October 19, 1990
    Date of Patent: January 28, 1992
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Tom J. Hirsch, Charles W. C. Lin, Ian Y. K. Yee
  • Patent number: 4981715
    Abstract: A method is described for patterning electroless plated metal on a polymer substrate. A substrate is first coated with a polymer suitable for complexing noble metal compounds. The substrate is then complexed with a noble metal compound, such as containing palladium, selectively irradiated to form the desired conductor pattern, and then etched so that the desired pattern remains. The substrate is subsequently placed in an electroless plating bath to form a metal pattern. Alternatively, before applying the noble metal compound, a substrate immersed in a polymer solution suitable for complexing a noble metal compound can be selectively irradiated to selectively deposit polymer on the substrate, followed by applying a noble metal compound and an electroless plating bath.
    Type: Grant
    Filed: March 13, 1990
    Date of Patent: January 1, 1991
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Tom J. Hirsch, Charles W. C. Lin