Abstract: Downlink traffic channel data rate options and methods of indicating to a wireless terminal a utilized downlink data rate option are described. The downlink traffic channel rate option for a segment is conveyed using an assignment signal and/or a block in the downlink traffic channel segment which is not used for user data. Downlink segment assignment signals in some implementations allocate fewer bits for rate option indication than are required to uniquely identify each option. In some implementations low rate options, e.g., using QPSK, are uniquely identified via assignment signals. Higher rate options, e.g., using QAM16 modulation, are conveyed via the distinct information block in the downlink traffic segment using a first coding/modulation method. Still higher rate options, e.g., using QAM16, QAM64, or QAM256, are conveyed via the information block in the segment using a second coding/modulation method which is applied to the rate option information.

Abstract: Methods and apparatus for allocating tones for communications in the strip-symbol periods in an OFDM system are described. In a strip-symbol, the signal is transmitted using the tones in a tone subset, which is selected from a predetermined set of tone subsets according to a fixed schedule sequence. Adjacent base stations and sectors use the same set of tone subsets but different schedule sequence to minimize the number of collisions between the tone subsets used in adjacent sectors and neighboring cells.

Abstract: A wireless terminal includes an uplink rate option indicator in the same uplink channel segment with data, the rate option indicator providing transmission rate information about the data transmitted in the segment. The indicator value is represented by an energy pattern within the segment. Different energy patterns correspond to different indicator values. The number of indicator values is less than the number of possible uplink data rate options supported by the wireless terminal. A single indicator value represents different uplink data rate options, at different times, as a function of a received maximum data rate option and/or type of assignment message. The maximum data rate option and/or assignment message was transmitted by the same base station receiving the indicator value; therefore, there is no ambiguity between wireless terminal and base station as to the interpretation of the uplink data rate option indicator value with respect to an individual uplink segment.

Abstract: A base station selects a maximum rate option indicator value for an uplink communications segment, e.g., uplink traffic channel segment, and transmits the selected indicator value, e.g., as part of the assignment message. The maximum rate option indicator value indicates to the wireless terminal a maximum allowed data rate option that the wireless terminal is permitted to use for the corresponding assigned uplink communications segment, the wireless terminal determining the actual uplink rate option used. Each uplink data rate option corresponds to: a number of information bits to be communicated in an uplink communication segment, a coding rate, and a modulation method. Some embodiments include multiple types of maximum uplink rate option indicators, e.g., a first type using a single bit and a second type using at least three bits. Different modulation methods are, in some embodiments, used for communicating the different types of maximum uplink rate option indicators.

Abstract: A device includes a zero symbol rate (ZSR) coding/modulation module and a second type coding/modulation module. Both modules generate modulation symbols to be conveyed using the same air link resources but with the non-zero ZSR symbols having a higher power level. The ZSR module generates a mixture of zero and non-zero modulation symbols. A ZSR modulation scheme communicates information using both the position of the non-zero modulation symbols and the phase and/or amplitude of the non-zero modulation symbols. Different ZSR schemes, implementing different ratios relating the number of zero symbols to the total number of symbols, can be associated with different low data rates while second module modulation schemes can be associated with different high data rates. Modulation symbols from two modules are in some embodiments, superimposed. In some embodiments, non-zero ZSR modulation symbols punch out second module modulation symbols which occupy the same air link resource.

Abstract: Different NAK signals are used to indicate different relative levels of success in regard to an unsuccessful attempt to decode a received signal. An ACK signal is used in the case of successful decoding. The device which generated and transmitted the original encoded signal receives the NAK signal and selects a portion of redundant information, e.g., additional error correction bits, to be transmitted based on the value of the NAK signal. If the NAK signal indicates a low level of decoding success indicating a relatively large number of errors in the decoded signal, a large set of redundant information is selected and transmitted. If the NAK signal indicates a relatively successful decoding, e.g., relatively few errors, a small set of redundant information is selected and transmitted. Where a small set of redundant information is transmitted new information can be transmitted with the redundant information.

Abstract: A composite signal includes a high power beacon signal and low power corresponding wideband synchronization signal and is communicated over a time interval exceeding a single OFDM transmission time interval. A base station transmits one or more different such composite broadcast signals in a recurring timing structure. Each different potential beacon signal, e.g., a single tone signal, is paired with a unique wideband synchronization signal. A wideband synchronization signal includes at least some predetermined null tones and at least some predetermined non-null tones. For a given wideband synchronization signal, the predetermined null tones carry predetermined modulation symbol values, A wireless terminal receives a composite signal, identifies a beacon, determines a corresponding known wideband synchronization signal, compares received to known wideband synchronization signals, and determines at least one of a timing adjustment, frequency adjustment and channel estimation.

Abstract: A location system for tracking assets within a terminal includes a Differential Global Positioning System (DGPS) reference receiver within the terminal that receives GPS signals and generates DGPS correction data. In one aspect, a roving receiver unit is carried by an asset to be tracked within the terminal. It includes a GPS receiver that receives GPS signals and the DGPS correction data from the DGPS reference receiver. A tag transmitter transmits a wireless RF signal containing GPS location data based on received GPS signals and DGPS correction data. At least one access point is positioned within the terminal for receiving the wireless RF signal from the tag transmitter. A processor is operatively connected to the at least one access point for receiving GPS location data and determining a location of the asset to be tracked.

Abstract: Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.

Abstract: The claimed subject matter relates to enabling antenna switching in a wireless terminal that has multiple receive antennas per receive chain via soft-demodulation and interleaving of concatenated code received in a strip channel. A coherent demodulation protocol may be performed to estimate an SNR for a first antenna during a first time period, and a non-coherent demodulation protocol may be utilized on the strip channel to estimate an SNR for at least one other antenna during a second time period. SNRs may be compared and the terminal may select the antenna with the highest SNR for a next transmission superslot.

Abstract: Methods and apparatus related to assignment in a wireless communications system are described. A mobile is assigned an identifier and a mask value, e.g., as part of a state transition message. The mobile uses the assigned identifier and/or the assigned mask value in determining whether assignments included in assignment messages, e.g., traffic channel assignment messages, are directed to the wireless terminal. Predetermined associations between assignment slots, assigned segments, and/or mask values are utilized to limit control signaling overhead. Different groups of segments are available for assignment to different wireless terminals as a function of mask values. Different types of assignment messages use different amounts of information bits to convey the assignment. Some types of assignments use a wireless terminal identifier, while other types of assignments use a wireless terminal identifier and a mask identifier. The mask identifier, e.g.

Abstract: A stream of modulation symbols from a zero symbol rate (ZSR) coding/modulation module and a stream of modulation symbols from another type of coding/modulation module are input into an interweaver module. The interweaver module mixes the two input streams when assigning modulation symbols to be communicated in a segment. If a ZSR modulation symbol is non-zero, the ZSR modulation symbol is allocated a transmission position. If the ZSR modulation symbol is a zero modulation symbol, the modulation symbol from the other coding/modulation module is allocated the transmission position. The non-zero modulation symbols from the ZSR module are higher in power than the non-zero modulation symbols from the other module, thus facilitating detection and recovery.

Abstract: Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages.

Abstract: Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.

Abstract: High throughput parallel LDPC decoders are designed and implemented using hierarchical design and layout optimization. In a first level of hierarchy, the node processors are grouped on the LDPC decoder chip, physically co-locating the processing elements in a small area. In a second level of hierarchy, clusters, e.g., subsets, of the processing elements are grouped together and a pipeline stage including pipeline registers is introduced on the boundaries between clusters. Register to register path propagating signals are keep localized as much as possible. The switching fabric coupling the node processors with edge message memory is partitioned into separate switches. Each separate switch is split into combinational switching layers. Design hierarchies are created for each layer, localizing the area where the interconnect is dense and resulting in short interconnect paths thus limiting signal delays in routing.

Abstract: In DEXA (dual energy x-ray absorptiometry), a system for automatically or nearly so identifying a region of interest in an AP (anterior/posterior) spinal image by processing the pixel values within a global region to find the lateral extent of the vertebra and the spaces between vertebra, and further processing the pixel values within the region of interest to derive estimates of bone parameters. In addition, also in DEXA, a system for automatically locating regions of interest in the hip.

Abstract: In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units.

Abstract: Frames including a packet boundary information field indicator and, optionally, packet boundary information field in addition to packet data are described. Methods and apparatus for generating and using such frames are also described. The packet boundary indicator indicates the presence or absence of at least one packet boundary information field in the frame. Frames with a payload that is fully occupied with data corresponding to a single packet do not include a packet boundary information field. The packet boundary information field indicates the location of a corresponding packet boundary and the type of boundary. One packet boundary information field is included in a frame for each boundary separating the data corresponding to different packets. By using packet boundary information fields to specify the location of packet boundaries, the need to parse an entire packet to identify the location of a packet boundary is avoided.

Abstract: Methods and apparatus for decoding codewords using message passing decoding techniques which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow decoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support message passing between the replicated copies of the small graph. Messages corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering messages, e.g.

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.