Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.

Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: A common mode rejection calibration scheme for use with a difference amplifier having an associated signal path. A signal is generated which varies with the common mode voltage of the differential input voltage applied to the amplifier. This signal is scaled and coupled into the signal path such that the scaled signal reduces the common-mode error that would otherwise be present in the difference amplifier's output.

Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: A common mode rejection calibration scheme for use with a difference amplifier having an associated signal path. A signal is generated which varies with the common mode voltage of the differential input voltage applied to the amplifier. This signal is scaled and coupled into the signal path such that the scaled signal reduces the common-mode error that would otherwise be present in the difference amplifier's output.

Abstract: A gain calibration system for an amplifier includes an amplifier having inputs and outputs and an analog to digital converter having inputs and an output. There is a voltage supply for providing a plurality of output voltages. A first switching circuit couples at least one of the output voltages to the inputs of the amplifier in a first phase. A second switching circuit couples the outputs of the amplifier to the inputs of the analog to digital converter in the first phase and couples the sum of all of the at least one output voltages to the input of the analog to digital converter in a second phase. A processor responsive to the outputs of the analog to digital converter in the first and second phases calculates a calibration factor to accommodate for amplifier gain error.

Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.

Abstract: A gain calibration system for an amplifier includes an amplifier having inputs and outputs and an analog to digital converter having inputs and an output. There is a voltage supply for providing a plurality of output voltages. A first switching circuit couples at least one of the output voltages to the inputs of the amplifier in a first phase. A second switching circuit couples the outputs of the amplifier to the inputs of the analog to digital converter in the first phase and couples the sum of all of the at least one output voltages to the input of the analog to digital converter in a second phase. A processor responsive to the outputs of the analog to digital converter in the first and second phases calculates a calibration factor to accommodate for amplifier gain error.

Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.