Patents by Inventor Tomasz Prokop
Tomasz Prokop has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9385893Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.Type: GrantFiled: February 10, 2014Date of Patent: July 5, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chaitanya Palusa, Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun, Adam B. Healey
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Patent number: 9294313Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.Type: GrantFiled: January 3, 2014Date of Patent: March 22, 2016Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Tomasz Prokop, Volodmyr Shvydun, Viswanath Annampedu, Amaresh V. Malipatil
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Publication number: 20150207648Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.Type: ApplicationFiled: February 10, 2014Publication date: July 23, 2015Applicant: LSI CorporationInventors: Chaitanya Palusa, Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun, Adam B. Healey
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Publication number: 20150195108Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.Type: ApplicationFiled: January 3, 2014Publication date: July 9, 2015Applicant: LSI CorporationInventors: Tomasz Prokop, Volodmyr Shvydun, Viswanath Annampedu, Amaresh V. Malipatil
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Patent number: 9077574Abstract: A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.Type: GrantFiled: March 27, 2014Date of Patent: July 7, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Adam B. Healey, Chaitanya Palusa, Tomasz Prokop, Volodymyr Shvydun
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Patent number: 9036729Abstract: A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.Type: GrantFiled: April 29, 2013Date of Patent: May 19, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Hiep Pham, Chaitanya Palusa, Tomasz Prokop, Adam Healey
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Patent number: 8976854Abstract: A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.Type: GrantFiled: February 28, 2014Date of Patent: March 10, 2015Assignee: LSI CorporationInventors: Adam B. Healey, Tomasz Prokop, Volodymyr Shvydun, Chaitanya Palusa
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Patent number: 8837570Abstract: Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M locations per slot and stores one set of M digitized symbols in one of the slots. The DFEs are responsive to common tap weight coefficients and produce parallel sets of M recovered data bits. Each DFE is first trained using sets of past digitized symbols loaded into a corresponding one of the prefix buffers and then processes digitized symbols stored in a corresponding one of the serial buffers.Type: GrantFiled: November 27, 2012Date of Patent: September 16, 2014Assignee: LSI CorporationInventors: Volodymyr Shvydun, Tomasz Prokop
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Publication number: 20140233668Abstract: A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.Type: ApplicationFiled: April 29, 2013Publication date: August 21, 2014Applicant: LSI CorporationInventors: Hiep Pham, Chaitanya Palusa, Tomasz Prokop, Adam Healey
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Patent number: 8804885Abstract: A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.Type: GrantFiled: December 19, 2005Date of Patent: August 12, 2014Assignee: Agere Systems LLCInventors: Rami Banna, Adriel P. Kind, Tomasz Prokop, Dominic W. Yip, Gongyu Zhou
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Patent number: 8804889Abstract: A receiver derives the desired data sampling clock phase by averaging the phase information of transitions before and after a data eye. The average of the phase information reduces data clock phase error due to variations in the phases of transitions in received data signals depending on the polarity and positions of the transitions.Type: GrantFiled: January 10, 2013Date of Patent: August 12, 2014Assignee: LSI CorporationInventors: Chaitanya Palusa, Tomasz Prokop
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Patent number: 8787439Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.Type: GrantFiled: March 13, 2012Date of Patent: July 22, 2014Assignee: LSI CorporationInventors: Chaitanya Palusa, Tomasz Prokop, Adam B. Healey, Ye Liu
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Publication number: 20140192935Abstract: A receiver derives the desired data sampling clock phase by averaging the phase information of transitions before and after a data eye. The average of the phase information reduces data clock phase error due to variations in the phases of transitions in received data signals depending on the polarity and positions of the transitions.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: LSI CORPORATIONInventors: Chaitanya Palusa, Tomasz Prokop
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Publication number: 20140146867Abstract: Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M locations per slot and stores one set of M digitized symbols in one of the slots. The DFEs are responsive to common tap weight coefficients and produce parallel sets of M recovered data bits. Each DFE is first trained using sets of past digitized symbols loaded into a corresponding one of the prefix buffers and then processes digitized symbols stored in a corresponding one of the serial buffers.Type: ApplicationFiled: November 27, 2012Publication date: May 29, 2014Applicant: LSI CORPORATIONInventors: Volodymyr Shvydun, Tomasz Prokop
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Patent number: 8582635Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.Type: GrantFiled: March 2, 2012Date of Patent: November 12, 2013Assignee: LSI CorporationInventors: Tomasz Prokop, Chaitanya Palusa
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Publication number: 20130243066Abstract: In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Inventors: Chaitanya Palusa, Tomasz Prokop, Adam B. Healey, Ye Liu
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Publication number: 20130230092Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.Type: ApplicationFiled: March 2, 2012Publication date: September 5, 2013Inventors: Tomasz Prokop, Chaitanya Palusa
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Patent number: 8462614Abstract: In one embodiment, a buffer-based method for generating codes (such as Orthogonal Variable Spreading Factor (OVSF) codes) for spreading and despreading data, without using a chip-rate counter. First, a buffer is populated with initial values based on a received spreading factor and desired code index. Next, a timing strobe is received, and the values in the buffer are changed upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe. Finally, a code sequence value is generated based on the values in the buffer.Type: GrantFiled: January 19, 2011Date of Patent: June 11, 2013Assignee: Agere Systems LLCInventors: Tomasz Prokop, Gongyu Zhou
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Publication number: 20110110399Abstract: In one embodiment, a buffer-based method for generating codes (such as Orthogonal Variable Spreading Factor (OVSF) codes) for spreading and despreading data, without using a chip-rate counter. First, a buffer is populated with initial values based on a received spreading factor and desired code index. Next, a timing strobe is received, and the values in the buffer are changed upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe. Finally, a code sequence value is generated based on the values in the buffer.Type: ApplicationFiled: January 19, 2011Publication date: May 12, 2011Applicant: Agere SystemsInventors: Tomasz Prokop, Gongyu Zhou
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Patent number: 7894327Abstract: A method of generating a code sequence comprises populating at least one buffer with initial values based on a received spreading factor and desired code index; receiving a timing strobe; changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and outputting at least one code sequence value based on the values in the at least one buffer. An apparatus for generating a code sequence comprises means for populating at least one buffer with initial values based on a received spreading factor and desired code index; means for receiving a timing strobe; means for changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and means for outputting at least one code sequence value based on the values in the at least one buffer.Type: GrantFiled: August 23, 2005Date of Patent: February 22, 2011Assignee: Agere Systems Inc.Inventors: Tomasz Prokop, Gongyu Zhou