Patents by Inventor Tomio Nagaoka

Tomio Nagaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6774467
    Abstract: Thin semiconductor device, especially a thin package, which reduces and achieves uniform mounting height, not requiring mounting of individual chips, improves manufacturing yield, without being affected by variation in chip thickness, enables testing alltogether, and process for producing same, the semiconductor mounted with back surface exposed upward, on top of an insulating substrate having throughholes in thickness direction, the area around semiconductor side surfaces being sealed by a resin layer, metal interconnections on the bottom surface of the substrate define bottom portions of throughholes of the substrate, a solder resist layer having throughholes in the thickness direction covers the bottom surface of metal interconnections and substrate, terminals extending downward from the active surface of the semiconductor are inserted into throughholes of the substrate, conductive filler fills gaps between the terminals and the throughholes of the substrate, and connection terminal and interconnections ar
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: August 10, 2004
    Assignee: Shinko Electric Industries Co., LTD
    Inventors: Michio Horiuchi, Takashi Kurihara, Tomio Nagaoka, Masao Aoki, Shigeru Mizuno
  • Publication number: 20010026010
    Abstract: A semiconductor device, in particular a thin semiconductor package, which reduces and simultaneously achieves a uniform mounting height, does not require complicated steps for mounting individual chips, improves the manufacturing yield, achieves a uniform height of the semiconductor device without being affected by the variation in thickness of the chip, and enables execution of an electrical test all together, and a process for production of the same, wherein a semiconductor is mounted, with its back surface exposed upward, on the top surface of an insulating tape substrate having through holes in the thickness direction, the area around the side surfaces of the semiconductor element is sealed by a sealing resin layer, metal interconnections formed on the bottom surface of the tape substrate define the bottom portions of the through holes of the tape substrate, a solder resist layer having through holes in the thickness direction covers the bottom surface of the metal interconnections and the tape substrate,
    Type: Application
    Filed: March 20, 2001
    Publication date: October 4, 2001
    Inventors: Michio Horiuchi, Takashi Kurihara, Tomio Nagaoka, Masao Aoki, Shigeru Mizuno