Patents by Inventor Tomisaburo Okumura

Tomisaburo Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4218764
    Abstract: A non-volatile memory control circuit for reprogramming non-volatile memory devices before their natural decay causes their "1" and "0" levels to become indistinguishable. Signals representing the memory states of the non-volatile memory devices are temporarily stored while the non-volatile memory devices are erased. After erasure the memory states are rewritten into the non-volatile memory devices. After rewriting, the control circuit is automatically reset. The erase/write operation is triggered by interrogating a second set of "parallel" non-volatile memory devices containing a predetermined data pattern, the interrogation occurring with a threshold detection level greater than that at which the memory levels of the primary non-volatile devices become indistinguishable.
    Type: Grant
    Filed: October 3, 1978
    Date of Patent: August 19, 1980
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Furuta, Tomisaburo Okumura
  • Patent number: 4177096
    Abstract: In manufacturing an insulated gate field effect transistor integrated circuit using both a self-alignment diffusion process and a non-self-alignment diffusion process, a mask is formed having a combined pattern of areas at which a subsequent self-alignment diffusion and a non-self-alignment diffusion will occur. An oxidation prevention layer for preventing thermal oxidation of a substrate is selectively formed on a semiconductor substrate using the prepared mask. Those areas of the semiconductor substrate which are not covered by the oxidation prevention layer are oxidized by thermal oxidation to form oxidized layers thereon, and impurities are diffused first in the areas of the substrate corresponding to the non-self-alignment portion of the mask pattern and subsequently in the areas of the substrate corresponding to the self-alignment portions of the mask pattern to build in an insulated gate field effect transistor network.
    Type: Grant
    Filed: January 25, 1977
    Date of Patent: December 4, 1979
    Assignee: Matsushita Electronics Corporation
    Inventors: Tomisaburo Okumura, Hiroshi Okazaki, Akira Tsuchitani
  • Patent number: 4113533
    Abstract: A method of making a MOS device, for instance, metal-oxide semiconductor type integrated circuit, is disclosed which comprises the following steps:Sequentially forming on a specified part of single crystal silicon substrate,Firstly, an oxide film,Secondly, a film to become a conductor film having a high-temperature-resistive nature, which does not melt at an impurity-diffusion temperature, serves as a diffusion mask and later serves as a gate electrode, for instance, polycrystalline silicon film; and thirdly, an oxidation-preventing film for preventing oxidation of said film to become the conductor film, wherein at least said conductor film and said overiding oxidation-preventing film have the same pattern so as to cover and prevent oxidation of said conductor film by said oxidation-preventing film, and thenDiffusing an impurity into the substrate from openings which are the parts other than those covered by said conductor film and said oxidation preventing film,The method being characterized by having a step
    Type: Grant
    Filed: January 28, 1977
    Date of Patent: September 12, 1978
    Assignee: Matsushita Electronics Corporation
    Inventors: Tomisaburo Okumura, Hiroshi Okazaki, Akira Tsuchitani, Seiji Ueda
  • Patent number: 3973271
    Abstract: A high-frequency transistor of planar structure having emitter and base regions of extremely fine structure to reduce the junction capacity. For the wire bond connection between said emitter or base region and an external lead wire, the transistor has the aluminium electrodes which swell and extend on the insulating film.
    Type: Grant
    Filed: April 28, 1971
    Date of Patent: August 3, 1976
    Assignee: Matsushita Electronics Corporation
    Inventors: Tomisaburo Okumura, Takatoshi Matsuo