Patents by Inventor Tomishi Takahashi

Tomishi Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9847300
    Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: December 19, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Nobutaka Sakai, Mamoru Otake, Koji Saito, Tomishi Takahashi
  • Publication number: 20160254228
    Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.
    Type: Application
    Filed: May 3, 2016
    Publication date: September 1, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Nobutaka SAKAI, Mamoru OTAKE, Koji SAITO, Tomishi TAKAHASHI
  • Patent number: 9362183
    Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: June 7, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Nobutaka Sakai, Mamoru Otake, Koji Saito, Tomishi Takahashi
  • Publication number: 20140017822
    Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 16, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Nobutaka SAKAI, Mamoru OTAKE, Koji SAITO, Tomishi TAKAHASHI
  • Patent number: 7416970
    Abstract: A manufacturing method is for providing an excellent wire bonding property in the manufacturing of a semiconductor device using an organic resin wiring substrate. In the manufacturing of the semiconductor device, a thermosonic wire bonding apparatus is used when the electrodes of a semiconductor element fixed to the principal surface of a substrate are connected to lines on the substrate with wires.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: August 26, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Tomishi Takahashi
  • Publication number: 20070212821
    Abstract: A manufacturing method is for providing an excellent wire bonding property in the manufacturing of a semiconductor device using an organic resin wiring substrate. In the manufacturing of the semiconductor device, a thermosonic wire bonding apparatus is used when the electrodes of a semiconductor element fixed to the principal surface of a substrate are connected to lines on the substrate with wires.
    Type: Application
    Filed: May 17, 2007
    Publication date: September 13, 2007
    Inventor: Tomishi Takahashi
  • Patent number: 7226815
    Abstract: A manufacturing method is for providing an excellent wire bonding property in the manufacturing of a semiconductor device using an organic resin wiring substrate. In the manufacturing of the semiconductor device, a thermosonic wire bonding apparatus is used when the electrodes of a semiconductor element fixed to the principal surface of a substrate are connected to lines on the substrate with wires.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: June 5, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tomishi Takahashi
  • Publication number: 20050176178
    Abstract: A manufacturing method is for providing an excellent wire bonding property in the manufacturing of a semiconductor device using an organic resin wiring substrate. In the manufacturing of the semiconductor device, a thermosonic wire bonding apparatus is used when the electrodes of a semiconductor element fixed to the principal surface of a substrate are connected to lines on the substrate with wires.
    Type: Application
    Filed: April 17, 2003
    Publication date: August 11, 2005
    Inventor: Tomishi Takahashi