Patents by Inventor Tomita YOSHIHIRO

Tomita YOSHIHIRO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240213171
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Inventors: Tomita YOSHIHIRO, Eric J. LI, Shawna M. LIFF, Javier A. FALCON, Joshua D. HEPPNER
  • Publication number: 20240063066
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, Tomita Yoshihiro, Adel A. Elsherbini, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Haris Khan Niazi, Yi Shi, Batao Zhang, Wenhao Li, Feras Eid
  • Publication number: 20200286834
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: Tomita YOSHIHIRO, Eric J. LI, Shawna M. LIFF, Javier A. FALCON, Joshua D. HEPPNER
  • Patent number: 10707171
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Tomita Yoshihiro, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
  • Publication number: 20180337135
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 22, 2018
    Inventors: Tomita YOSHIHIRO, Eric J. LI, Shawna M. LIFF, Javier A. FALCON, Joshua D. HEPPNER