Patents by Inventor Tommy Pan
Tommy Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220157775Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.Type: ApplicationFiled: January 11, 2022Publication date: May 19, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Chih SHEN, Jen-Chuan CHEN, Tommy PAN
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Patent number: 11222866Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.Type: GrantFiled: June 12, 2017Date of Patent: January 11, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
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Publication number: 20170278823Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.Type: ApplicationFiled: June 12, 2017Publication date: September 28, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Chih SHEN, Jen-Chuan CHEN, Tommy PAN
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Patent number: 9698120Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.Type: GrantFiled: November 22, 2013Date of Patent: July 4, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
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Publication number: 20140087519Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.Type: ApplicationFiled: November 22, 2013Publication date: March 27, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
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Patent number: 8618645Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.Type: GrantFiled: February 24, 2010Date of Patent: December 31, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
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Patent number: 8446000Abstract: A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.Type: GrantFiled: May 24, 2010Date of Patent: May 21, 2013Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan, Hui-Shan Chang, Chia-Lin Hung
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Publication number: 20110121442Abstract: A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.Type: ApplicationFiled: May 24, 2010Publication date: May 26, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan, Hui-Shan Chang, Chia-Lin Hung
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Publication number: 20110074004Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the side walls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the side walls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.Type: ApplicationFiled: February 24, 2010Publication date: March 31, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
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Publication number: 20100327465Abstract: A package process is provided. First, a semiconductor substrate is disposed on a carrier, in which a surface of the carrier has an adhesive layer and the semiconductor substrate is bonded to the carrier by the adhesive layer. Next, a chip is bonded on the semiconductor substrate by flip chip technique and a first underfill is formed between the chip and the semiconductor substrate to encapsulate a plurality of first conductive bumps at the bottom of the chip. Then, a first molding compound is formed on the semiconductor substrate. The first molding compound at least encapsulates the side surface of the chip and the first underfill. Finally, the semiconductor substrate together with the chip and the first molding compound located thereon are separated from the adhesive layer of the carrier to form an array package structure.Type: ApplicationFiled: August 10, 2009Publication date: December 30, 2010Applicant: Advanced Semiconductor Engineering, Inc.Inventors: CHI-CHIH SHEN, Jen-Chuan Chen, Tommy Pan
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Patent number: 7791211Abstract: A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.Type: GrantFiled: August 15, 2008Date of Patent: September 7, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jen-Chuan Chen, Chi-Chih Shen, Hui-Shan Chang, Tommy Pan
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Publication number: 20090127706Abstract: A chip package structure and process are provided; the structure includes a substrate, a chip, a solder layer and at least a stud bump. The substrate has at least a contact pad, and the chip has an active surface where at least a bonding pad is disposed. The stud bump is disposed on the bonding pad of the chip or on the contact pad of the substrate, and the stud bump joints with the solder layer to fix the chip on the substrate. The stud bump is made of gold-silver alloy containing silver below 15% by weight.Type: ApplicationFiled: October 9, 2008Publication date: May 21, 2009Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Hui-Shan Chang, Tommy Pan
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Publication number: 20090102047Abstract: A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.Type: ApplicationFiled: August 15, 2008Publication date: April 23, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jen-Chuan Chen, Chi-Chih Shen, Hui-Shan Chang, Tommy Pan