Patents by Inventor Tomoaki Ikegami
Tomoaki Ikegami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373611Abstract: First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.Type: GrantFiled: March 22, 2012Date of Patent: June 21, 2016Assignee: SOCIONEXT INC.Inventors: Hidetoshi Nishimura, Tomoaki Ikegami
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Patent number: 9142539Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: December 17, 2014Date of Patent: September 22, 2015Assignee: SOCIONEXT INC.Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Publication number: 20150137248Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: ApplicationFiled: December 17, 2014Publication date: May 21, 2015Inventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
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Patent number: 8946824Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: April 15, 2014Date of Patent: February 3, 2015Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Publication number: 20140225164Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: PANASONIC CORPORATIONInventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
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Patent number: 8748987Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: October 24, 2013Date of Patent: June 10, 2014Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Patent number: 8698273Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.Type: GrantFiled: December 13, 2012Date of Patent: April 15, 2014Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Hidetoshi Nishimura, Kazuyuki Nakanishi
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Publication number: 20140077307Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: ApplicationFiled: October 24, 2013Publication date: March 20, 2014Applicant: PANASONIC CORPORATIONInventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
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Patent number: 8598668Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: February 14, 2013Date of Patent: December 3, 2013Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Patent number: 8399928Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: July 8, 2011Date of Patent: March 19, 2013Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Patent number: 8368225Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.Type: GrantFiled: May 23, 2011Date of Patent: February 5, 2013Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Hidetoshi Nishimura, Kazuyuki Nakanishi
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Publication number: 20120256234Abstract: First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.Type: ApplicationFiled: March 22, 2012Publication date: October 11, 2012Applicant: PANASONIC CORPORATIONInventors: HIDETOSHI NISHIMURA, TOMOAKI IKEGAMI
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Publication number: 20110284964Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: ApplicationFiled: July 8, 2011Publication date: November 24, 2011Applicant: PANASONIC CORPORATIONInventors: Tomoaki IKEGAMI, Kazuyuki Nakanishi, Masaki Tamaru
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Publication number: 20110221067Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.Type: ApplicationFiled: May 23, 2011Publication date: September 15, 2011Applicant: Panasonic CorporationInventors: Tomoaki IKEGAMI, Hidetoshi NISHIMURA, Kazuyuki NAKANISHI
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Patent number: 8004014Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.Type: GrantFiled: August 17, 2009Date of Patent: August 23, 2011Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Hidetoshi Nishimura, Kazuyuki Nakanishi
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Publication number: 20100308377Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.Type: ApplicationFiled: August 17, 2010Publication date: December 9, 2010Inventors: Kazuyuki NAKANISHI, Hidetoshi Nishimura, Tomoaki Ikegami
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Patent number: 7800140Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.Type: GrantFiled: March 14, 2008Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Kazuyuki Nakanishi, Hidetoshi Nishimura, Tomoaki Ikegami
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Publication number: 20100001404Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.Type: ApplicationFiled: August 17, 2009Publication date: January 7, 2010Applicant: PANASONIC CORPORATIONInventors: Tomoaki Ikegami, Hidetoshi Nishimura, Kazuyuki Nakanishi
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Publication number: 20080224176Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.Type: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Inventors: Kazuyuki Nakanishi, Hidetoshi Nishimura, Tomoaki Ikegami
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Publication number: 20070200238Abstract: In a semiconductor integrated circuit apparatus formed by a core cell constituting a circuit function and a power wiring cell including a power wiring, a metal of a power wiring unit cell constituting the power wiring cell is formed to take a shape of T, and the power wiring unit cell is disposed adjacently, thereby forming a serial power wiring. The core cell and the power wiring cell are connected to each other through a metal wiring in the core cell in which coordinates in a horizontal direction are preset, and a power signal is thus supplied.Type: ApplicationFiled: February 8, 2007Publication date: August 30, 2007Inventors: Tomoaki Ikegami, Hidetoshi Nishimura