Patents by Inventor Tomoaki Masaki

Tomoaki Masaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971633
    Abstract: An electrode structure includes: a plurality of pixel electrodes arranged separately from each other; and a plurality of dielectric layers laminated in a first direction with respect to the plurality of pixel electrodes, in which the plurality of dielectric layers includes: a first dielectric layer that spreads over the plurality of pixel electrodes in a direction intersecting with the first direction; and a second dielectric layer that includes dielectric material having a refractive index higher than that of the first dielectric layer, sandwiches the first dielectric layer together with the plurality of pixel electrodes, and has a slit at a position overlapping space between pixel electrodes adjacent when viewed from the first direction.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 30, 2024
    Assignees: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, SONY GROUP CORPORATION
    Inventors: Takashi Sakairi, Tomoaki Honda, Tsuyoshi Okazaki, Keiichi Maeda, Chiho Araki, Katsunori Dai, Shunsuke Narui, Kunihiko Hikichi, Kouta Fukumoto, Toshiaki Okada, Takuma Matsuno, Yuu Kawaguchi, Yuuji Adachi, Koichi Amari, Hideki Kawaguchi, Seiya Haraguchi, Takayoshi Masaki, Takuya Fujino, Tadayuki Dofuku, Yosuke Takita, Kazuhiro Tamura, Atsushi Tanaka
  • Patent number: 7304763
    Abstract: Sets of pixel data obtained by dividing entered image data into a predetermined number of items of data are stored in storage means in a predetermined order, and conversion processing is executed for obtaining individual items of pixel data of an output image by applying predetermined processing to the stored pixel data. When the conversion processing is executed, it is determined whether a set of pixel data to be stored in the storage means next is used in conversion processing, and control is carried out in such a manner that a set of pixel data determined not to be used in conversion processing will not be stored in the storage means. As a result, processing for storing unnecessary data not used in conversion processing can be eliminated, thereby making it possible to raise the overall speed of image processing.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: December 4, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomoaki Masaki
  • Publication number: 20030218774
    Abstract: Sets of pixel data obtained by dividing entered image data into a predetermined number of items of data are stored in storage means in a predetermined order, and conversion processing is executed for obtaining individual items of pixel data of an output image by applying predetermined processing to the stored pixel data. When the conversion processing is executed, it is determined whether a set of pixel data to be stored in the storage means next is used in conversion processing, and control is carried out in such a manner that a set of pixel data determined not to be used in conversion processing will not be stored in the storage means. As a result, processing for storing unnecessary data not used in conversion processing can be eliminated, thereby making it possible to raise the overall speed of image processing.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 27, 2003
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tomoaki Masaki
  • Patent number: 6373589
    Abstract: An apparatus, having a simple configuration capable of reading data from DRAM in hyper-page mode at high speed. When a change in row address is detected while reading the data, storing of data read after the detection and changing of address are prohibited, and the read data is discarded. When the number of accesses has reached a predetermined number, the processing is terminated. When necessary data have not been stored, the row address is changed, and remaining data to be read is read in the hyper-page mode. Further, when it is determined that the necessary data have been stored before the number of accesses reaches the predetermined number, setting of data read thereafter is prohibited, as well as changing of address is also prohibited, thereby discarding the read data.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: April 16, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomoaki Masaki
  • Publication number: 20010012125
    Abstract: An apparatus, having a simple configuration capable of reading data from DRAM in hyper page mode at high speed. When a change in row address is detected while reading the data, storing of data read after the detection and changing of address are prohibited, and the read data is discarded. When the number of accesses has reached a predetermined number, the processing is terminated. When necessary data have not been stored, the row address is changed, and remaining data to be read is read in the hyper page mode. Further, when it is determined that the necessary data have been stored before the number of accesses reaches the predetermined number, setting of data read thereafter is prohibited, as well as changing of address is also prohibited, thereby discarding the read data.
    Type: Application
    Filed: February 24, 1998
    Publication date: August 9, 2001
    Inventor: TOMOAKI MASAKI
  • Patent number: 5936645
    Abstract: On the basis of an encoder output pulse generated by useing a linear encoder film provided along a moving path of a carriage, ink ejection timing is determined. Then, the ink ejection timing is set at a timing derived by dividing a period of the output pulse by three, and the pulse period to be divided is the immediately preceding pulse period. By this, even with open loop control of driving of a carriage motor, high precision ejecting position control can be performed.
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: August 10, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeji Niikura, Tomoaki Masaki, Akiyoshi Shimoda
  • Patent number: 5652607
    Abstract: Power is supplied to a CPU without regard to an on/off-state of a power switch. In the off-state, the CPU renders a control signal, which indicates that an apparatus does not accept data, to an active state or a high impedance state to inform to a host. When data is received, the state is switched to the on-state for recording operation. The received data is stored in a memory, and when the state is switched to the on-state, the data is read from the memory for recording operation. In this manner, loss of record data due to data transmission from the host in the off-state of the power switch is prevented.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: July 29, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomoaki Masaki