Patents by Inventor Tomoaki Nimura

Tomoaki Nimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time
    Patent number: 7557428
    Abstract: A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: July 7, 2009
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Hiroyasu Kunitomo, Tomoaki Nimura, Isamu Kuno, Ryuji Ariyoshi
  • Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time
    Publication number: 20060157822
    Abstract: A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 20, 2006
    Applicant: Kawasaki Microelectronics, Inc.
    Inventors: Hiroyasu Kunitomo, Tomoaki Nimura, Isamu Kuno, Ryuji Ariyoshi