Patents by Inventor Tomoaki Shino
Tomoaki Shino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240088152Abstract: A semiconductor device of an embodiment includes N-wells and P-wells extending in a first direction and alternately arranged in a second direction orthogonal to the first direction; and a dummy gate formed above the N-wells and the P-wells so as to extend across at least one boundary between an N-well and a P-well that are adjacent to each other, the dummy gate being not connected to a wire, in which the dummy gate is formed in a region other than an end portion in the first direction of, among the N-wells and the P-wells, a well that has a width smaller than a predetermined threshold in the second direction.Type: ApplicationFiled: July 31, 2023Publication date: March 14, 2024Applicant: Kioxia CorporationInventors: Tomoaki SHINO, Mitsuhiro NOGUCHI, Takayuki TOBA
-
Patent number: 11462556Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: October 15, 2020Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
-
Patent number: 11227915Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.Type: GrantFiled: August 18, 2020Date of Patent: January 18, 2022Assignee: KIOXIA CORPORATIONInventors: Ryuta Tezuka, Mitsuhiro Noguchi, Tomoaki Shino
-
Publication number: 20210305368Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.Type: ApplicationFiled: August 18, 2020Publication date: September 30, 2021Inventors: Ryuta TEZUKA, Mitsuhiro NOGUCHI, Tomoaki SHINO
-
Patent number: 11069710Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.Type: GrantFiled: May 11, 2020Date of Patent: July 20, 2021Assignee: Toshiba Memory CorporationInventors: Hiroyasu Tanaka, Tomoaki Shino
-
Publication number: 20210028185Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: October 15, 2020Publication date: January 28, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
-
Patent number: 10840257Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: February 11, 2019Date of Patent: November 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
-
Publication number: 20200273883Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Applicant: Toshiba Memory CorporationInventors: Hiroyasu TANAKA, Tomoaki SHINO
-
Patent number: 10685976Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.Type: GrantFiled: November 1, 2018Date of Patent: June 16, 2020Assignee: Toshiba Memory CorporationInventors: Hiroyasu Tanaka, Tomoaki Shino
-
Publication number: 20200066743Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: February 11, 2019Publication date: February 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
-
Publication number: 20190074293Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.Type: ApplicationFiled: November 1, 2018Publication date: March 7, 2019Applicant: Toshiba Memory CorporationInventors: Hiroyasu Tanaka, Tomoaki Shino
-
Patent number: 10134755Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer including a first portion and a second portion between the substrate and a second insulating layer, and the second insulating layer covering the circuit. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The second insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the second insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the first insulating layer.Type: GrantFiled: March 17, 2017Date of Patent: November 20, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyasu Tanaka, Tomoaki Shino
-
Publication number: 20180083029Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.Type: ApplicationFiled: March 17, 2017Publication date: March 22, 2018Applicant: Toshiba Memory CorporationInventors: Hiroyasu TANAKA, Tomoaki SHINO
-
Patent number: 8026553Abstract: This disclosure concerns a memory comprising a semiconductor layer extending in a first direction; a source; a drain; a body between the source and the drain; a bit-line extending in the first direction; a first gate-dielectric on a first side-surface of the body; a first gate-electrode on the first side-surface of the body via the first gate dielectric film; a first gate line extending in the first direction, connected to a bottom of the first gate-electrode, and formed integratedly with the first gate-electrode using same material; a second gate dielectric on a second side-surface of the body; a second gate-electrode on the second side surface of the body via the second gate dielectric film; and a second gate line extending in a second direction crossing the first direction, connected to an upper portion of the second gate-electrode, and formed integratedly with the second gate-electrode using same material.Type: GrantFiled: May 2, 2008Date of Patent: September 27, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Tomoaki Shino
-
Patent number: 7977738Abstract: A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.Type: GrantFiled: July 2, 2009Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Minami, Takashi Ohsawa, Tomoaki Shino, Takeshi Hamamoto, Akihiro Nitayama
-
Patent number: 7911000Abstract: A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between the first and the second diffusion layers; a first gate dielectric film provided on an outer side surface of the U-shaped layer; a first gate electrode provided on the first gate dielectric film; a second gate dielectric film provided on an inner side surface of the U-shaped layer; a second gate electrode provided on the second gate dielectric film; a bit line contact connecting the bit line to the first diffusion layer; a source line contact connecting the source line to the second diffusion layer, wherein cells adjacent in the first direction alternately share the bit line contact and the source line contact.Type: GrantFiled: January 27, 2009Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Tomoaki Shino
-
Publication number: 20110062527Abstract: In one embodiment, a semiconductor apparatus is disclosed. The apparatus includes: an element-isolation insulating film formed on a major surface of a semiconductor layer, the element-isolation insulating film having a first opening and a second opening; an n-type MOSFET provided in the first opening; and a p-type MOSFET provided in the first opening. An upper face of a portion of the element-isolation insulating film adjacent to a source/drain region of the n-type MOSFET is positioned below an upper face of the source/drain region of the n-type MOSFET. An upper face of a portion of the element-isolation insulating film adjacent to a source/drain region of the p-type MOSFET is positioned above an upper face of the source/drain region of the p-type MOSFET.Type: ApplicationFiled: September 7, 2010Publication date: March 17, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Tomoaki SHINO, Mitsuhiro Noguchi
-
Patent number: 7847322Abstract: This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a first dielectric film provided on the semiconductor substrate; two Fins provided on the first dielectric film and made of a semiconductor material; a second dielectric film provided on facing inner side surfaces among side surfaces of the two Fins; a third dielectric film provided on outer side surfaces among side surfaces of the two Fins; a gate electrode provided via the second dielectric film between the inner side surfaces of the two Fins; and a plate electrode provided via the third dielectric film on the outer side surfaces of the two Fins, wherein the two Fins, the gate electrode, and the plate electrode are included in one memory cell.Type: GrantFiled: May 25, 2007Date of Patent: December 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamada, Tomoaki Shino
-
Patent number: 7795658Abstract: A semiconductor memory device includes a supporting substrate including semiconductor materials. The memory device also includes an insulation film provided above the supporting substrate. The memory device further includes a first diffusion layer provided on the insulation film. In addition, the memory device includes a second diffusion layer provided on the insulation film. The memory device additionally includes a body region provided between the first diffusion layer and the second diffusion layer. The body region is in an electrically floating state and accumulates or releases electric charges for storing data. Also, the memory device includes a semiconductor layer penetrating the insulation film and electrically connecting the second diffusion layer to the supporting substrate to release electric charges from the second diffusion layer. Further, the memory device includes a gate insulation film provided on the body region.Type: GrantFiled: February 21, 2007Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Tomoaki Shino
-
Publication number: 20100085813Abstract: This disclosure concerns a driving method of a memory having cells of floating body type which comprises executing, during a write operation, a first cycle of applying a first potential to the bit lines corresponding to the first selected cells and of applying a second potential to the selected word line to write first data; executing, during the write operation, a second cycle of applying a third potential to the bit lines corresponding to a second selected cell among the first selected memory cells and of applying a fourth potential to the selected word line to write second data, wherein the second potential is a potential biased to a reversed side against the polarity of the carriers with reference to potentials of the source and the first potential, and the fourth potential is a biased to same polarity as the polarity of the carriers with reference to the potentials of the source and the third potential.Type: ApplicationFiled: June 25, 2008Publication date: April 8, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tomoaki Shino