Abstract: A thermal management circuit has a LT circuit including a reservoir tank and a battery circuit not including the reservoir tank. The thermal management system includes an ECU that controls a five-way valve to switch a plurality of modes with regard to a flow path for a heat medium in the thermal management circuit. The plurality of modes include a first mode (first circuit mode) and a second mode (third circuit mode). The first mode is a mode in which the LT circuit and the battery circuit are connected together in series. The second mode is a mode in which the LT circuit and the battery circuit are connected together in parallel and part of the heat medium flowing in the battery circuit flows to the LT circuit via the five-way valve.

Abstract: According to one embodiment, a semiconductor memory device includes a first circuit, multiple second circuits, and a first number of first channels connected to the first circuit. One or more second circuits are connected to each first channel. The control circuit is connected to the semiconductor memory device via a second channel. The control circuit generates multiple first access requests each for one of the second circuits. The control circuit determines order of execution of the first access requests to allow concurrent execution of a second number of first access requests designating two or more of the second circuits connected to different first channels. The control circuit executes in parallel the second number of data transfers responsive to the second number of first access requests via the second channel at a transfer rate the second number of times a transfer rate of one of the first number of first channels.

Abstract: An anomaly determination device, an anomaly determination method, and a memory medium for a water pump are provided. An acquisition process acquires an input variable of a map from image data obtained by capturing an outer surface of the water pump. Execution circuitry obtains provisional determination results from maps, respectively. The provisional determination results are respectively obtained by executing the provisional determination processes for output variables output from the maps. A determination finalizing process treats, as a majority of the provisional determination results, a final determination result indicating whether coolant has leaked out of the water pump.

Abstract: According to an embodiment, a semiconductor memory device includes a first chip, a second chip, and a third chip. In a case where a first command sequence including a first address indicating the first chip is received from the first device, the third chip performs transfer of a second command sequence including the first address via the first channel and transfer of a third command sequence including a second address indicating the second chip via the second channel. After a first time elapses from completion of the transfers of the second and third command sequences, the third chip transfers first read enable signals to the first and second channels in parallel, and acquires pieces of first status information in parallel via the first and second channels. The third chip outputs first status information to the first device.

Abstract: A cylinder block is provided. A water jacket spacer is disposed inside a water jacket of the cylinder block. The water jacket includes a first passage connecting an inlet to a discharge section, and a second passage connecting the inlet to the discharging portion. The first passage is shorter than the second passage. A spacer plate of the water jacket spacer is provided with a restricting portion. The restricting portion is located in the first passage. A width dimension of the restricting portion is larger than a width dimension in a cylinder-radial direction of the spacer plate, the cylinder-radial direction being a radial direction of the cylinder. A width dimension of the restricting portion is smaller than a width dimension in the cylinder-radial direction of the water jacket.

Abstract: According to one embodiment, in a semiconductor device, a first chip is electrically connected to a terminal to which a signal from a host is input. The first chip is electrically connected to a second chip and to a third chip in parallel with the second chip. The first chip includes a first buffer memory and a second buffer memory. The first buffer memory corresponds to the second chip. The second buffer memory corresponds to the third chip. The second chip includes a third buffer memory. The third chip includes a fourth buffer memory. A capacity of the first buffer memory is equal to or larger than a capacity of the third buffer memory. A capacity of the second buffer memory is equal to or larger than a capacity of the fourth buffer memory.

Abstract: An anomaly determination device, an anomaly determination method, and a memory medium for a water pump are provided. An acquisition process acquires an input variable of a map from image data obtained by capturing an outer surface of the water pump. Execution circuitry obtains provisional determination results from maps, respectively. The provisional determination results are respectively obtained by executing the provisional determination processes for output variables output from the maps. A determination finalizing process treats, as a majority of the provisional determination results, a final determination result indicating whether coolant has leaked out of the water pump.

Abstract: A semiconductor device includes terminals connectable to a host, first and second bridge chips connected to the terminals, first chips connected to the first bridge chip, and second chips connected to the second bridge chip. The terminals includes a first terminal through which a first signal designating a bridge chip is transmitted. The first bridge chip is configured to enable signal transmission to at least one of the first chips when the first signal designates the first bridge chip, and disable the signal transmission to the first chips when the first signal does not designate the first bridge chip. The second bridge chip is configured to enable signal transmission to at least one of the second chips when the first signal designates the second bridge chip, and disable the signal transmission to the second chips when the first signal does not designate the second bridge chip.

Abstract: A semiconductor integrated circuit includes a register, a first interface circuit, an oscillation circuit that generates a first clock, a pll circuit, a control circuit, and a second interface circuit. The register stores numerical information representing a data size. The first interface circuit receives, from a first device, a first timing signal for data transfer. Responding to receipt of the first timing signal, the control circuit inputs the first timing signal to the pll circuit and counts the number of toggles of the first timing signal. When a counted number of toggles of the first timing signal matches a value corresponding to the numerical information, the control circuit inputs the first clock to the pll circuit. The second interface circuit transmits, to a second device, the first timing signal or a second timing signal, which corresponds to a second clock generated based on the first clock by the pll circuit.

Abstract: According to one embodiment, in a semiconductor device, a first chip is electrically connected to a terminal to which a signal from a host is input. The first chip is electrically connected to a second chip and to a third chip in parallel with the second chip. The first chip includes a first buffer memory and a second buffer memory. The first buffer memory corresponds to the second chip. The second buffer memory corresponds to the third chip. The second chip includes a third buffer memory. The third chip includes a fourth buffer memory. A capacity of the first buffer memory is equal to or larger than a capacity of the third buffer memory. A capacity of the second buffer memory is equal to or larger than a capacity of the fourth buffer memory.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: A semiconductor device includes a terminal group configured to receive a first signal and a second signal from a host, a first chip electrically connected to the terminal group, and a second chip electrically connected to the terminal group. The first chip is configured to, in response to reception of the first signal, transmit a third signal corresponding to the first signal to the second chip. The first chip is configured to, when the first chip has received the second signal before the first signal, refrain from transmitting the third signal to the second chip.

Abstract: A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: A semiconductor device includes a terminal group configured to receive a first signal and a second signal from a host, a first chip electrically connected to the terminal group, and a second chip electrically connected to the terminal group. The first chip is configured to, in response to reception of the first signal, transmit a third signal corresponding to the first signal to the second chip. The first chip is configured to, when the first chip has received the second signal before the first signal, refrain from transmitting the third signal to the second chip.

Abstract: According to one embodiment, an electronic apparatus includes an interface circuit connectable to a first signal line, a second signal line, and a third signal line, and a controller. Before transmitting data using the first signal line, the controller is configured to transmit a first command using the first signal line while transmitting a first control signal using the second signal line, and transmit a first address using the first signal line while transmitting a second control signal using the third signal line. While transmitting the data using the first signal line, the controller is configured to transmit at least one of a second command and a second address using the second signal line and the third signal line.

Abstract: A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: A semiconductor integrated circuit includes a register, a first interface circuit, an oscillation circuit that generates a first clock, a pll circuit, a control circuit, and a second interface circuit. The register stores numerical information representing a data size. The first interface circuit receives, from a first device, a first timing signal for data transfer. Responding to receipt of the first timing signal, the control circuit inputs the first timing signal to the pll circuit and counts the number of toggles of the first timing signal. When a counted number of toggles of the first timing signal matches a value corresponding to the numerical information, the control circuit inputs the first clock to the pll circuit. The second interface circuit transmits, to a second device, the first timing signal or a second timing signal, which corresponds to a second clock generated based on the first clock by the pll circuit.

Abstract: A display device has a display panel provided with a plurality of light emitting elements 10 including a light emitting part 30, and a lens member 50 through which light emitted from the light emitting part 30 passes, in which when a distance (an offset amount) between a normal LN passing through a center of the light emitting part 30 and a normal LN? passing through a center of the lens member 50 is defined as D0, a value of the distance (offset amount) D0 is not 0 in at least some of the light emitting elements 10 provided in the display panel.