Abstract: There is provided a graphics processing system that allows decompression of a compressed texture with high efficiency. The graphics processing system includes: a main memory; and a graphics processing unit, in which the graphics processing unit includes a run length decoding section adapted to run-length-decode a compressed texture, and a reciprocal spatial frequency conversion section adapted to restore the texture by performing reciprocal spatial frequency conversion on the run-length-decoded texture, and the main memory includes a texture pool adapted to partially cache the restored texture.

Abstract: There is provided a graphics processor that allows decompression of a compressed texture with high efficiency. The graphics processor includes: a main memory; and a graphics processing unit, in which the graphics processing unit includes a run length decoding section adapted to run-length-decode a compressed texture, and a reciprocal spatial frequency conversion section adapted to restore the texture by performing reciprocal spatial frequency conversion on the run-length-decoded texture, and the main memory includes a texture pool adapted to partially cache the restored texture.

Abstract: Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g.

Abstract: Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g.

Abstract: Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g.

Abstract: Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g.

Abstract: A method is disclosed which may include issuing a plurality of instructions in a processing pipeline of a first processor within a multiprocessor system; determining whether a second processor in the multiprocessor system is in at least one of a running state and a waiting state; and transferring at least one of the instructions to execution stages of a processing pipeline of the second processor and bypassing at least one earlier stage of the processing pipeline of the second processor, when the second processor is in the waiting state.

Abstract: It is an object of the present invention to provide an arithmetic logic unit that can perform a sum-of-products operation in a reduced number of processing cycles without carrying out data transfer and additions even in obtaining a single result from a plurality of divided input data words. Data words X and Y are input. A product of the high-order bits of X and Y is calculated using first decoder 511, first selector 521, first partial product generator 531 and first full adder 541. A product of the low-order bits of X and Y is also calculated using second decoder 512, second selector 522, second partial product generator 532 and second full adder 542. These products are adaptively shifted at a shifter 55 and then added up with a fed back data word Z at a third full adder 56 and a carry-propagation adder 58. In this manner, the data word Z, representing the result of the sum-of-products operation, is obtained.